Patents by Inventor Madhukar Tallam

Madhukar Tallam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10169254
    Abstract: Embodiments of techniques and systems for increasing efficiencies in computing systems using virtual memory are described. In embodiments, instructions which are located in two memory pages in a virtual memory system, such that one of the pages does not permit execution of the instructions located therein, are identified and then executed under temporary permissions that permit execution of the identified instructions. In various embodiments, the temporary permissions may come from modified virtual memory page tables, temporary virtual memory page tables which allow for execution, and/or emulators which have root access. In embodiments, per-core virtual memory page tables may be provided to allow two cores of a computer processor to operate in accordance with different memory access permissions. In embodiments, a physical page permission table may be utilized to provide for maintenance and tracking of per-physical-page memory access permissions. Other embodiments may be described and claimed.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: January 1, 2019
    Assignee: Intel Corporation
    Inventors: Ramesh Thomas, Kuo-Lang Tseng, Ravi L. Sahita, David M. Durham, Madhukar Tallam
  • Patent number: 10073986
    Abstract: Embodiments of apparatus, computer-implemented methods, systems, and computer-readable media are described herein for a virtual machine manager, wherein the virtual machine manager is configured to selectively employ different views with different permissions to map guest physical memory of a virtual machine of the apparatus to host physical memory of the apparatus, to regulate access to and protect different portions of an application of the virtual machine that resides in different portions of the physical memory. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Harshawardhan Vipat, Ravi L. Sahita, Roshni Chatterjee, Madhukar Tallam
  • Patent number: 9965403
    Abstract: Embodiments of techniques and systems for increasing efficiencies in computing systems using virtual memory are described. In embodiments, instructions which are located in two memory pages in a virtual memory system, such that one of the pages does not permit execution of the instructions located therein, are identified and then executed under temporary permissions that permit execution of the identified instructions. In various embodiments, the temporary permissions may come from modified virtual memory page tables, temporary virtual memory page tables which allow for execution, and/or emulators which have root access. In embodiments, per-core virtual memory page tables may be provided to allow two cores of a computer processor to operate in accordance with different memory access permissions. In embodiments, a physical page permission table may be utilized to provide for maintenance and tracking of per-physical-page memory access permissions. Other embodiments may be described and claimed.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: May 8, 2018
    Assignee: Intel Corporation
    Inventors: Ramesh Thomas, Kuo-Lang Tseng, Ravi L. Sahita, David M. Durham, Madhukar Tallam
  • Publication number: 20170344494
    Abstract: Embodiments of techniques and systems for increasing efficiencies in computing systems using virtual memory are described. In embodiments, instructions which are located in two memory pages in a virtual memory system, such that one of the pages does not permit execution of the instructions located therein, are identified and then executed under temporary permissions that permit execution of the identified instructions. In various embodiments, the temporary permissions may come from modified virtual memory page tables, temporary virtual memory page tables which allow for execution, and/or emulators which have root access. In embodiments, per-core virtual memory page tables may be provided to allow two cores of a computer processor to operate in accordance with different memory access permissions. In embodiments, a physical page permission table may be utilized to provide for maintenance and tracking of per-physical-page memory access permissions. Other embodiments may be described and claimed.
    Type: Application
    Filed: August 2, 2017
    Publication date: November 30, 2017
    Inventors: Ramesh Thomas, Kuo-Lang Tseng, Ravi L. Sahita, David M. Durham, Madhukar Tallam
  • Patent number: 9747123
    Abstract: Technologies for multi-level virtualization include a computing device having a processor that supports a root virtualization mode and a non-root virtualization mode. A non-root hypervisor determines whether it is executed under control of a root hypervisor, and if so, registers a callback handler and trigger conditions with the root hypervisor. The non-root hypervisor hosts one or more virtual machines. In response to a virtual machine exit, the root hypervisor determines whether a callback handler has been registered for the virtual machine exit reason and, if so, evaluates the trigger conditions associated with the callback handler. If the trigger conditions are satisfied, the root hypervisor invokes the callback handler. The callback handler may update a virtual virtualization support object based on changes made by the root hypervisor to a virtualization support object. The root hypervisor may invoke the callback handler in the non-root virtualization mode. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: August 29, 2017
    Assignee: Intel Corporation
    Inventors: Jun Nakajima, Asit K. Mallick, Harshawardhan Vipat, Madhukar Tallam, Manohar R. Castelino
  • Publication number: 20170090963
    Abstract: Technologies for multi-level virtualization include a computing device having a processor that supports a root virtualization mode and a non-root virtualization mode. A non-root hypervisor determines whether it is executed under control of a root hypervisor, and if so, registers a callback handler and trigger conditions with the root hypervisor. The non-root hypervisor hosts one or more virtual machines. In response to a virtual machine exit, the root hypervisor determines whether a callback handler has been registered for the virtual machine exit reason and, if so, evaluates the trigger conditions associated with the callback handler. If the trigger conditions are satisfied, the root hypervisor invokes the callback handler. The callback handler may update a virtual virtualization support object based on changes made by the root hypervisor to a virtualization support object. The root hypervisor may invoke the callback handler in the non-root virtualization mode. Other embodiments are described and claimed.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: Jun Nakajima, Asit K. Mallick, Harshawardhan Vipat, Madhukar Tallam, Manohar R. Castelino
  • Patent number: 9436576
    Abstract: Methods and apparatus are disclosed to capture error conditions in lightweight virtual machine managers. A disclosed example method includes defining a shared memory structure between the VMM and a virtual machine (VM), when the VM is spawned by the VMM, installing an abort handler on the VM associated with a vector value, in response to detecting an error, transferring VMM state information to the shared memory structure, and invoking the abort handler on the VM to transfer contents of the shared memory structure to a non-volatile memory.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: September 6, 2016
    Assignee: Intel Corporation
    Inventors: Bing Zhu, Peng Zou, Madhukar Tallam, Luhai Chen, Kai Wang
  • Patent number: 9372812
    Abstract: Embodiments of systems, apparatuses, and methods for determining if an instruction of a virtual machine is allowed to modify a protected memory region are described. In some embodiments, a system detects an indication of an attempt by the instruction to write to the protected memory region. In addition, the system determines if the instruction is allowed to write to the protected memory region based on a starting address and data length of the instruction. Furthermore, if the instruction is allowed to write to the protected memory region, the system updates the protected memory region with the instruction results.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: June 21, 2016
    Assignee: Intel Corporation
    Inventors: Kuo-Lang Tseng, Baohong Liu, Ritu Sood, Manohar Ruben Castelino, Madhukar Tallam
  • Publication number: 20160162698
    Abstract: Embodiments of apparatus, computer-implemented methods, systems, and computer-readable media are described herein for a virtual machine manager, wherein the virtual machine manager is configured to selectively employ different views with different permissions to map guest physical memory of a virtual machine of the apparatus to host physical memory of the apparatus, to regulate access to and protect different portions of an application of the virtual machine that resides in different portions of the physical memory. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: February 12, 2016
    Publication date: June 9, 2016
    Inventors: Harshawardhan Vipat, Ravi L. Sahita, Roshni Chatterjee, Madhukar Tallam
  • Patent number: 9298639
    Abstract: Embodiments of an invention for controlling access to groups of memory pages in a virtualized environment are disclosed. In one embodiment, a processor includes a virtualization unit and a memory management unit. The virtualization unit is to transfer control of the processor to a virtual machine. The memory management unit is to perform, in response to an attempt to execute on the virtual machine an instruction stored on a first page, a page walk through a paging structure to find a second page and to allow access to the second page without exiting the virtual machine based at least in part on a bit being set in a leaf level entry corresponding to the second page in the paging structure and a corresponding bit being set in each entry corresponding to the first page in each level of the paging structure.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: March 29, 2016
    Assignee: Intel Corporation
    Inventors: Baohong Liu, Ritu Sood, Kuo-Lang Tseng, Madhukar Tallam
  • Patent number: 9292679
    Abstract: Embodiments of apparatus, computer-implemented methods, systems, and computer-readable media are described herein for a virtual machine manager, wherein the virtual machine manager is configured to selectively employ different views with different permissions to map guest physical memory of a virtual machine of the apparatus to host physical memory of the apparatus, to regulate access to and protect different portions of an application of the virtual machine that resides in different portions of the physical memory. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: March 22, 2016
    Assignee: INTEL CORPORATION
    Inventors: Harshawardhan Vipat, Ravi L. Sahita, Roshni Chatterjee, Madhukar Tallam
  • Publication number: 20150301947
    Abstract: Embodiments of an invention for controlling access to groups of memory pages in a virtualized environment are disclosed. In one embodiment, a processor includes a virtualization unit and a memory management unit. The virtualization unit is to transfer control of the processor to a virtual machine. The memory management unit is to perform, in response to an attempt to execute on the virtual machine an instruction stored on a first page, a page walk through a paging structure to find a second page and to allow access to the second page without exiting the virtual machine based at least in part on a bit being set in a leaf level entry corresponding to the second page in the paging structure and a corresponding bit being set in each entry corresponding to the first page in each level of the paging structure.
    Type: Application
    Filed: June 30, 2015
    Publication date: October 22, 2015
    Applicant: Intel Corporation
    Inventors: Baohong Liu, Ritu Sood, Kuo-Lang Tseng, Madhukar Tallam
  • Patent number: 9141559
    Abstract: Embodiments of techniques and systems for increasing efficiencies in computing systems using virtual memory are described. In embodiments, instructions which are located in two memory pages in a virtual memory system, such that one of the pages does not permit execution of the instructions located therein, are identified and then executed under temporary permissions that permit execution of the identified instructions. In various embodiments, the temporary permissions may come from modified virtual memory page tables, temporary virtual memory page tables which allow for execution, and/or emulators which have root access. In embodiments, per-core virtual memory page tables may be provided to allow two cores of a computer processor to operate in accordance with different memory access permissions. in embodiments, a physical page permission table may be utilized to provide for maintenance and tracking of per-physical-page memory access permissions. Other embodiments may be described and claimed.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: September 22, 2015
    Assignee: Intel Corporation
    Inventors: Ramesh Thomas, Kuo-Lang Tseng, Ravi L. Sahita, David M. Durham, Madhukar Tallam
  • Publication number: 20150242333
    Abstract: Embodiments of techniques and systems for increasing efficiencies in computing systems using virtual memory are described. In embodiments, instructions which are located in two memory pages in a virtual memory system, such that one of the pages does not permit execution of the instructions located therein, are identified and then executed under temporary permissions that permit execution of the identified instructions. In various embodiments, the temporary permissions may come from modified virtual memory page tables, temporary virtual memory page tables which allow for execution, and/or emulators which have root access. In embodiments, per-core virtual memory page tables may be provided to allow two cores of a computer processor to operate in accordance with different memory access permissions. In embodiments, a physical page permission table may be utilized to provide for maintenance and tracking of per-physical-page memory access permissions. Other embodiments may be described and claimed.
    Type: Application
    Filed: May 11, 2015
    Publication date: August 27, 2015
    Inventors: Ramesh Thomas, Kuo-Lang Tseng, Ravi L. Sahita, David M. Durham, Madhukar Tallam
  • Patent number: 9098427
    Abstract: Embodiments of an invention for controlling access to groups of memory pages in a virtualized environment are disclosed. In one embodiment, a processor includes a virtualization unit and a memory management unit. The virtualization unit is to transfer control of the processor to a virtual machine. The memory management unit is to perform, in response to an attempt to execute on the virtual machine an instruction stored on a first page, a page walk through a paging structure to find a second page and to allow access to the second page without exiting the virtual machine based at least in part on a bit being set in a leaf level entry corresponding to the second page in the paging structure and a corresponding bit being set in each entry corresponding to the first page in each level of the paging structure.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: August 4, 2015
    Assignee: Intel Corporation
    Inventors: Baohong Liu, Ritu Sood, Kuo-Lang Tseng, Madhukar Tallam
  • Publication number: 20140245430
    Abstract: Embodiments of apparatus, computer-implemented methods, systems, and computer-readable media are described herein for a virtual machine manager, wherein the virtual machine manager is configured to selectively employ different views with different permissions to map guest physical memory of a virtual machine of the apparatus to host physical memory of the apparatus, to regulate access to and protect different portions of an application of the virtual machine that resides in different portions of the physical memory. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: May 7, 2014
    Publication date: August 28, 2014
    Inventors: Harshawardhan Vipat, Ravi L. Sahita, Roshni Chatterjee, Madhukar Tallam
  • Publication number: 20140201422
    Abstract: Embodiments of systems, apparatuses, and methods for determining if an instruction of a virtual machine is allowed to modify a protected memory region are described. In some embodiments, a system detects an indication of an attempt by the instruction to write to the protected memory region. In addition, the system determines if the instruction is allowed to write to the protected memory region based on a starting address and data length of the instruction. Furthermore, if the instruction is allowed to write to the protected memory region, the system updates the protected memory region with the instruction results.
    Type: Application
    Filed: December 22, 2011
    Publication date: July 17, 2014
    Inventors: Kuo-Lang Tseng, Baohong Liu, Ritu Sood, Manohar Ruben Castelino, Madhukar Tallam
  • Patent number: 8726404
    Abstract: Embodiments of apparatus, computer-implemented methods, systems, and computer-readable media are described herein for a virtual machine manager, wherein the virtual machine manager is configured to selectively employ different views with different permissions to map guest physical memory of a virtual machine of the apparatus to host physical memory of the apparatus, to regulate access to and protect different portions of an application of the virtual machine that resides in different portions of the physical memory. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: May 13, 2014
    Assignee: Intel Corporation
    Inventors: Harshawardhan Vipat, Ravi L. Sahita, Roshni Chatterjee, Madhukar Tallam
  • Patent number: 8719546
    Abstract: Embodiments of techniques and systems for using substitute virtualized-memory page tables are described. In embodiments, a virtual machine monitor (VMM) may determine that a virtualized memory access to be performed by an instruction executing on a guest software virtual machine is not allowed in accordance with a current virtualized-memory page table (VMPT). The VMM may select a substitute VMPT that permits the virtualized memory access, In scenarios where a data access length for the instruction is known, the substitute VMPT may include full execute, read, and write permissions for the entire guest software address space. In scenarios where a data access length for the instruction is not known, the substitute VMPT may include less than full execute, read, and write permissions for the entire guest software address space, and may be modified to allow the requested virtualized memory access. Other embodiments may be described and claimed.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: May 6, 2014
    Assignee: Intel Corporation
    Inventors: Baohong Liu, Manohar R. Castelino, Kuo-Lang Tseng, Ritu Sood, Madhukar Tallam
  • Publication number: 20140006877
    Abstract: Methods and apparatus are disclosed to capture error conditions in lightweight virtual machine managers. A disclosed example method includes defining a shared memory structure between the VMM and a virtual machine (VM), when the VM is spawned by the VMM, installing an abort handler on the VM associated with a vector value, in response to detecting an error, transferring VMM state information to the shared memory structure, and invoking the abort handler on the VM to transfer contents of the shared memory structure to a non-volatile memory.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Inventors: Bing Zhu, Peng Zou, Madhukar Tallam, Luhai Chen, Kai Wang