Abstract: A method and apparatus for repairing a memory is provided. At least one memory is tested using a production test pattern. After the production test, a passing or failing status is determined for each memory tested. This determination may be made using a built-in repair analysis (BIRA) program. After the analysis the location of each failing memory is determined. A fuse register pattern is then determined for the failing memory, and at least one fuse is blown to repair the failed memory. The repair utilizes at least one of the redundant memories present in the semiconductor device. The apparatus includes a semiconductor device having repairable memories, a fuse programmable read-only memory (FPROM) that contains multiple redundant memories, and a fuse box memory repair apparatus that is in communication with the FRPOM and the multiple repairable memories.

Abstract: A method and apparatus for repairing a memory is provided. At least one memory is tested using a production test pattern. After the production test, a passing or failing status is determined for each memory tested. This determination may be made using a built-in repair analysis (BIRA) program. After the analysis the location of each failing memory is determined. A fuse register pattern is then determined for the failing memory, and at least one fuse is blown to repair the failed memory. The repair utilizes at least one of the redundant memories present in the semiconductor device. The apparatus includes a semiconductor device having repairable memories, a fuse programmable read-only memory (FPROM) that contains multiple redundant memories, and a fuse box memory repair apparatus that is in communication with the FRPOM and the multiple repairable memories.

Abstract: A method and apparatus for adaptive test time reduction is provided. The method begins with running a predetermined number of structural tests on wafers or electronic chips. Pass/fail data is collected once the predetermined number of structural tests have been run. This pass/fail data is then used to determine which of the predetermined number of structural tests are consistently passed. The consistently passed tests are then grouped into slices within the test vectors. Once the grouping has been performed, the consistently passed tests are skipped when testing future production lots of the wafers or electronic chips. A sampling rate may be modulated if it is determined that adjustments in the tests performed are needed. In addition, a complement of the tests performed on the wafers may be performed on the electronic chips to ensure complete test coverage.