Abstract: In an embodiment, a processor may include a mesh network and a clock regulation circuit. The mesh network may include multiple mesh stops to operate based on a mesh clock signal. Each mesh stop may include a bandwidth counter to transmit a bandwidth count in response to a pulse of a synchronization signal. The clock regulation circuit may be to: receive a plurality of bandwidth counts from the plurality of mesh stops; aggregate the plurality of bandwidth counts to obtain an aggregated bandwidth value; determine a cycle stealing value based at least on a comparison of the aggregated bandwidth value to at least one threshold value; and gate the mesh clock signal based on the determined cycle stealing value. Other embodiments are described and claimed.

Abstract: Provided are systems, apparatuses, and techniques for managing processor system power and performance based on operational metrics, hardware capabilities, and/or other parameters.

Abstract: In one embodiment, a processor includes: at least one first core to execute instructions; at least one second core to execute instructions; and a control circuit coupled to the at least one first core and the at least one second core. The control circuit may be configured to: receive workload telemetry information regarding a workload for execution on the processor; determine a QoS distribution based at least in part on the workload telemetry information; receive a predicted workload type, the predicted workload type based at least in part on the QoS distribution; and cause at least one of the at least one first core or the at least one second core to be parked based on the predicted workload type and the QoS distribution. Other embodiments are described and claimed.

Abstract: An apparatus and method are described for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores and power management circuitry to associate a plurality of performance values and a plurality of efficiency values with the plurality of cores. In some implementations, each core is associated with at least one performance value and at least one efficiency value. The performance values and efficiency values are used by a scheduler for scheduling threads on the plurality of cores. Some implementations include dynamic core configuration hardware logic coupled to or integral to the power management circuitry to resolve a plurality of configuration requests into a consolidated request for updating one or more performance values of the plurality of performance values and/or one or more efficiency values of the plurality of efficiency values.

Abstract: Embodiments herein relate to selecting cores in a processor using a core mask. In one aspect, a computing device includes different types of cores arranged in one or more processors. The core types are different in terms of performance and power consumption. A core mask is provided which indicates the number of cores which are selected to be active for each core type. A driver can receive a gear setting, which represents a first preference for higher performance or reduced power consumption. A slider value, which represents a second preference for higher performance or reduced power consumption, is provided based on the gear setting and a core utilization percentage and/or foreground activity percentage. A core mask is selected based on the slider value and the current workload type. The first preference can guide, without dictating, a decision of which cores are selected.

Abstract: In an embodiment, a processor may include a core domain comprising a plurality of processing cores, an uncore domain comprising an internal network, and a processor power management circuit. The processor power management circuit may be to: receive scalability hint values from the processing cores; determine a total core gain and a total uncore gain based at least in part on the scalability hint values; and distribute a frequency budget between the core domain and the uncore domain based at least in part on the total core gain and the total uncore gain. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor may include a mesh network and a clock regulation circuit. The mesh network may include multiple mesh stops to operate based on a mesh clock signal. Each mesh stop may include a bandwidth counter to transmit a bandwidth count in response to a pulse of a synchronization signal. The clock regulation circuit may be to: receive a plurality of bandwidth counts from the plurality of mesh stops; aggregate the plurality of bandwidth counts to obtain an aggregated bandwidth value; determine a cycle stealing value based at least on a comparison of the aggregated bandwidth value to at least one threshold value; and gate the mesh clock signal based on the determined cycle stealing value. Other embodiments are described and claimed.

Abstract: Various embodiments provide apparatuses, systems, and methods for bandwidth-based control of phase count in a voltage regulator. The techniques described herein may be used with a voltage regulator that supply power to a data circuit that processes data traffic. The voltage regulator includes a plurality of phases to generate an output voltage that is provided to the data circuit. A control circuit determines a bandwidth of the data traffic that is handled by the data circuit and control a number of the phases that are active based on the determined bandwidth. Other embodiments may be described and claimed.

Abstract: A method and system for finding an exact match for an N-bit wide address. A system for finding an exact match for an N-bit wide address in every clock cycle includes a label extraction module and one or more pipeline blocks. The label extraction module extracts K bits from the N-bit wide address. The extracted K bits are used by pipeline block 1 as a key to directly lookup a base node of multibit trie. The base node is included in first lookup table (LUT) and first LUT is configured to store pointers to leaf nodes of multibit trie. A pipeline block 2 searches a current LUT for match on next Q bits of remaining (N?K) bits to retrieve a current pointer. Then, pipeline block (N?K)/Q finds the exact match by retrieving a unique search index matching remaining (N?K) bits when the current pointer is not empty.

Abstract: A method and system for finding an exact match for an N-bit wide address. A system for finding an exact match for an N-bit wide address in every clock cycle includes a label extraction module and one or more pipeline blocks. The label extraction module extracts K bits from the N-bit wide address. The extracted K bits are used by pipeline block 1 as a key to directly lookup a base node of multibit trie. The base node is included in first lookup table (LUT) and first LUT is configured to store pointers to leaf nodes of multibit trie. A pipeline block 2 searches a current LUT for match on next Q bits of remaining (N?K) bits to retrieve a current pointer. Then, pipeline block (N?K)/Q finds the exact match by retrieving a unique search index matching remaining (N?K) bits when the current pointer is not empty.