Abstract: An integrated clock gate (ICG) includes an OR-AND-INVERT gate to receive a first enable and a second enable; a first inverter coupled to the output of the OR-AND-INVERT; a first NAND gate coupled to the output of the first inverter; a second NAND gate coupled to the output of the OR-AND-INVERT; and a second inverter to provide a clock which is gated based on logic values of the first enable and/or the second enable, wherein an output of the second inverter is received as input by the OR-AND-INVERT-gate. The ICG circuit reduces capacitance of input clk pin, which translates to lower switching power when clock is gated and reduction in dynamic power of clock network, since buffers in clock tree driving the ICG cells can be downsized. The ICG cell has the smallest transistor count (and area) when compared to existing ICG cell topologies.

Abstract: Systems and methods of a configuration distribution microservice include reception of a first data structure comprising first configuration data of a first type and associated with a first tenant of a first microservice, determination of one or more other microservices associated with the first tenant and the first type of configuration data, and transmission of an instruction to the determined one or more other microservices to deploy the first configuration data.

Abstract: Systems and methods of a configuration distribution microservice include reception of a first data structure comprising first configuration data of a first type and associated with a first tenant of a first microservice, determination of one or more other microservices associated with the first tenant and the first type of configuration data, and transmission of an instruction to the determined one or more other microservices to deploy the first configuration data.