Abstract: Embodiments of the present invention provide a system, method, and program product for domain based resource isolation in multi-core systems. A computing device determines an operation being attempted on a workload request identified with a first domain identifier. The computing device determines a processor core identified with a second domain identifier. In response to determining that processor cores identified with the second domain identifier can service workload requests identified with the first domain identifier, the computing device deploys the workload request to the processor core for servicing.

Abstract: An approach to virtualizing a coherent memory hardware accelerator is provided comprising creating a segment table for a client logical partition (LPAR), wherein a virtual address space is reserved in the segment table, receiving an Input/Output (I/O) request to use the coherent memory hardware accelerator, generating an I/O operation associated with the I/O request, wherein the I/O operation is passed to the coherent memory hardware accelerator, receiving a map request from the coherent memory hardware accelerator, creating an entry in the reserved virtual address space in the segment table, creating a hardware page table map request for mapping a memory address associated with the client LPAR and returning the reserved virtual address space to the coherent memory hardware accelerator, wherein the coherent memory hardware accelerator has remote direct memory access to memory associated with the client LPAR for performing an acceleration of one or more processes.

Abstract: An approach to virtualizing a coherent memory hardware accelerator is provided comprising creating a segment table for a client logical partition (LPAR), wherein a virtual address space is reserved in the segment table, receiving an Input/Output (I/O) request to use the coherent memory hardware accelerator, generating an I/O operation associated with the I/O request, wherein the I/O operation is passed to the coherent memory hardware accelerator, receiving a map request from the coherent memory hardware accelerator, creating an entry in the reserved virtual address space in the segment table, creating a hardware page table map request for mapping a memory address associated with the client LPAR and returning the reserved virtual address space to the coherent memory hardware accelerator, wherein the coherent memory hardware accelerator has remote direct memory access to memory associated with the client LPAR for performing an acceleration of one or more processes.

Abstract: Provided are techniques for the orderly shutdown of a node within a cluster in the event of asymmetric topology maps, comprising receiving, at a first node, a plurality of heartbeats, each heartbeat corresponding to a particular, corresponding other node in the cluster and comprising information on a topological map corresponding to each particular other node's view of the cluster generating, by the first node, a topological map of the cluster based upon the information comprising the heartbeats; comparing the topological map of the cluster and the topological maps corresponding to each node; in response to a determination that the topological maps of the duster and each node are not in agreement, determining the connectivity of the first node with respect to the cluster and in respond to a determination that the first node has the lowest connectivity within the cluster, shutting down the first node.

Abstract: An approach to virtualizing a coherent memory hardware accelerator is provided comprising creating a segment table for a client logical partition (LPAR), wherein a virtual address space is reserved in the segment table, receiving an Input/Output (I/O) request to use the coherent memory hardware accelerator, generating an I/O operation associated with the I/O request, wherein the I/O operation is passed to the coherent memory hardware accelerator, receiving a map request from the coherent memory hardware accelerator, creating an entry in the reserved virtual address space in the segment table, creating a hardware page table map request for mapping a memory address associated with the client LPAR and returning the reserved virtual address space to the coherent memory hardware accelerator, wherein the coherent memory hardware accelerator has remote direct memory access to memory associated with the client LPAR for performing an acceleration of one or more processes.

Abstract: An approach to virtualizing a coherent memory hardware accelerator is provided comprising creating a segment table for a client logical partition (LPAR), wherein a virtual address space is reserved in the segment table, receiving an Input/Output (I/O) request to use the coherent memory hardware accelerator, generating an I/O operation associated with the I/O request, wherein the I/O operation is passed to the coherent memory hardware accelerator, receiving a map request from the coherent memory hardware accelerator, creating an entry in the reserved virtual address space in the segment table, creating a hardware page table map request for mapping a memory address associated with the client LPAR and returning the reserved virtual address space to the coherent memory hardware accelerator, wherein the coherent memory hardware accelerator has remote direct memory access to memory associated with the client LPAR for performing an acceleration of one or more processes.

Abstract: Disclosed aspects include managing the access of flash memory by a computer system. A physical memory address space which includes a flash memory portion is established. The flash memory portion may correspond to an input/output memory range. An access request may be detected with respect to the physical memory address space. Using a load-store technique to process the access request, the flash memory portion of the physical memory address space may be accessed.

Abstract: Disclosed aspects include managing the access of flash memory by a computer system. A physical memory address space which includes a flash memory portion is established. The flash memory portion may correspond to an input/output memory range. An access request may be detected with respect to the physical memory address space. Using a load-store technique to process the access request, the flash memory portion of the physical memory address space may be accessed.

Abstract: An approach is presented that provides computer clustering support across geographical boundaries. Inter-node communications are managed in a cluster by having each node operate at the network device driver (NDD) level within the kernel. Multiple types of NDD are utilized (Ethernet, SAN, DISK etc.) to provide redundancy so that nodes can reliably exchange heartbeat. To align with this architecture, for remote nodes, a pseudo NDD is used over Transmission Control Protocol (TCP) based communication interface to work along side other NDDs. Thus, the same packet which is sprayed over the NDDs pertaining to local nodes can be sprayed over the TCPSOCK NDD interface for remote nodes. Nodes (local or remote) receive the same packet and reassemble and process it in the same manner.

Abstract: An approach is presented that provides computer clustering support across geographical boundaries. Inter-node communications are managed in a cluster by having each node operate at the network device driver (NDD) level within the kernel. Multiple types of NDD are utilized (Ethernet, SAN, DISK etc.) to provide redundancy so that nodes can reliably exchange heartbeat. To align with this architecture, for remote nodes, a pseudo NDD is used over Transmission Control Protocol (TCP) based communication interface to work along side other NDDs. Thus, the same packet which is sprayed over the NDDs pertaining to local nodes can be sprayed over the TCPSOCK NDD interface for remote nodes. Nodes (local or remote) receive the same packet and reassemble and process it in the same manner.

Abstract: Mechanisms are provided, in a data processing system comprising a plurality of nodes, each node being a computing device, for controlling access to a critical section of code. These mechanisms send, by a sender node of the data processing system, an access request for requesting access to the critical section of code. The critical section of code is a portion of code that accesses a shared resource. The mechanisms receive, in the sender node, from a plurality of receiver nodes in the data processing system, responses to the access request. Each response in the responses includes a number of active nodes perceived by a corresponding receiver node that transmitted the response. The mechanisms control, by the sender node, access to the critical section of code based on the number of active nodes identified in each of the responses received from the receiver nodes.

Abstract: Mechanisms are provided, in a data processing system comprising a plurality of nodes, each node being a computing device, for controlling access to a critical section of code. These mechanisms send, by a sender node of the data processing system, an access request for requesting access to the critical section of code. The critical section of code is a portion of code that accesses a shared resource. The mechanisms receive, in the sender node, from a plurality of receiver nodes in the data processing system, responses to the access request. Each response in the responses includes a number of active nodes perceived by a corresponding receiver node that transmitted the response. The mechanisms control, by the sender node, access to the critical section of code based on the number of active nodes identified in each of the responses received from the receiver nodes.

Abstract: Disclosed aspects include managing the access of flash memory by a computer system. A physical memory address space which includes a flash memory portion is established. The flash memory portion may correspond to an input/output memory range. An access request may be detected with respect to the physical memory address space. Using a load-store technique to process the access request, the flash memory portion of the physical memory address space may be accessed.

Abstract: Disclosed aspects include managing the access of flash memory by a computer system. A physical memory address space which includes a flash memory portion is established. The flash memory portion may correspond to an input/output memory range. An access request may be detected with respect to the physical memory address space. Using a load-store technique to process the access request, the flash memory portion of the physical memory address space may be accessed.

Abstract: A virtual machine of an information handling system (IHS) initializes an operating system to provide partition file system memory management during application execution. The operating system employs multiple partitions that include one or more applications for execution within the virtual machine. A file system tool identifies write operations to a global file system and generates local and common file system information. The file system tool populates the local file systems that include delta local file systems and differential file systems with write operation data. The file system tool may generate stackable common delta file system information to store write operation data common to two or more partitions that employ executing applications. The file system tool may combine or separate stackable common delta file system information to provide improvements in virtual machine memory utilization.

Abstract: A virtual machine of an information handling system (IHS) initializes an operating system to provide partition file system memory management during application execution. The operating system employs multiple partitions that include one or more applications for execution within the virtual machine. A file system tool identifies write operations to a global file system and generates local and common file system information. The file system tool populates the local file systems that include delta local file systems and differential file systems with write operation data. The file system tool may generate stackable common delta file system information to store write operation data common to two or more partitions that employ executing applications. The file system tool may combine or separate stackable common delta file system information to provide improvements in virtual machine memory utilization.

Abstract: Embodiments of the present invention provide a system, method, and program product for domain based resource isolation in multi-core systems. A computing device determines an operation being attempted on a workload request identified with a first domain identifier. The computing device determines a processor core identified with a second domain identifier. In response to determining that processor cores identified with the second domain identifier can service workload requests identified with the first domain identifier, the computing device deploys the workload request to the processor core for servicing.

Abstract: Mechanisms are provided, in a data processing system comprising a plurality of nodes, each node being a computing device, for controlling access to a critical section of code. These mechanisms send, by a sender node of the data processing system, an access request for requesting access to the critical section of code. The critical section of code is a portion of code that accesses a shared resource. The mechanisms receive, in the sender node, from a plurality of receiver nodes in the data processing system, responses to the access request. Each response in the responses includes a number of active nodes perceived by a corresponding receiver node that transmitted the response. The mechanisms control, by the sender node, access to the critical section of code based on the number of active nodes identified in each of the responses received from the receiver nodes.

Abstract: Mechanisms are provided, in a data processing system comprising a plurality of nodes, each node being a computing device, for controlling access to a critical section of code. These mechanisms send, by a sender node of the data processing system, an access request for requesting access to the critical section of code. The critical section of code is a portion of code that accesses a shared resource. The mechanisms receive, in the sender node, from a plurality of receiver nodes in the data processing system, responses to the access request. Each response in the responses includes a number of active nodes perceived by a corresponding receiver node that transmitted the response. The mechanisms control, by the sender node, access to the critical section of code based on the number of active nodes identified in each of the responses received from the receiver nodes.

Abstract: Methods, apparatuses, and computer program products are provided for locking access to data storage shared by a plurality of compute nodes. Embodiments include maintaining, by a compute node, a queue of requests from requesting compute nodes of the plurality of compute nodes for access to the data storage, wherein possession of the queue represents possession of a mutual-exclusion lock on the data storage, the mutual-exclusion lock indicating exclusive permission for access to the data storage; and conveying, based on the order of requests in the queue, possession of the queue from the compute node to a next requesting compute node when the compute node no longer requires exclusive access to the data storage.