Abstract: An apparatus for controlling a sensor over a network includes a transceiver and a processor. The transceiver is configured to communicate over the network. The processor is configured to receive or generate control data for controlling a sensor, the sensor being connected to the network by a peer device. The processor is further configured to wake-up a link with the peer device in accordance with a schedule, and, during a time period in the schedule in which the link with the peer device is awake, to send to the peer device a packet comprising the control data.

Abstract: An apparatus for controlling a sensor over a network includes a transceiver and a processor. The transceiver is configured to communicate over a network. The processor is configured to receive or generate control data for controlling a sensor connected to the network, to generate a packet including (i) the control data and (ii) a trigger timestamp indicative of a future time at which the control data is to be provided to the sensor, and to transmit the packet using the transceiver over the network.

Abstract: Machine implemented method and system are provided. A processor for a computing device allocates an address range with an address to write to an intermediate storage location. The processor configures a device communicating with the computing device for writing information at the intermediate storage location and at a plurality of storage locations. The computing device sends the address for the intermediate storage location with data that needs to be written at one of the plurality of storage locations with an identifier identifying the one of the plurality of storage locations; and the device first writes the data at the intermediate storage location and then updates the one of the plurality of storage locations identified by the identifier.

Abstract: An adapter for high speed multiple buffer allocation is provided. The adapter is configured with logic to search a data buffer availability vector corresponding to data buffer storage elements from low priority to high priority and from high priority to low priority in parallel thereby enabling multiple data buffers to be located in a single path and reducing the impact of pipelining.