Patents by Inventor Madhusudhan Rangarajan

Madhusudhan Rangarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10649832
    Abstract: Embodiments of the claimed invention include a computing device having a host processor for executing a firmware environment and a manageability controller. The firmware environment reserves a frame buffer in main memory and loads a graphics protocol driver to provide the frame buffer to an operating system of the computing device. The operating system renders graphical images to the frame buffer using a graphics driver. The manageability controller reads the graphical image from the frame buffer and may transmit the graphical image to a remote computing device. In response to a fatal error of the computing device, the manageability controller may store the graphical image to a non-volatile storage device. The host processor may assert a host reset signal in response to the fatal error, and the manageability controller may send an acknowledgment to the host processor after storing the graphical image. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Kasper Wszolek, Janusz P. Jurski, Piotr Kwidzinski, Robert C. Swanson, Madhusudhan Rangarajan
  • Publication number: 20190138359
    Abstract: Devices, systems, and methods for offloading data service operations from an application critical path are disclosed. A storage service control apparatus can include a compute resource interface configured to communicatively couple to a compute resource, a memory interface configured to communicatively couple to a memory resource, an out of band (oob) channel interface configured to communicatively couple to an oob channel, and a data service controller communicatively coupled to the oob channel interface. The data service controller is configured to identify a data service operation to be performed by the compute resource on data stored in the memory resource, load a data service agent configured to facilitate the data service operation, and perform the data service operation on the data to generate serviced data via the data service agent over the oob channel by an oob compute resource, thus freeing the compute resource from performing the data service operation.
    Type: Application
    Filed: August 27, 2018
    Publication date: May 9, 2019
    Applicant: Intel Corporation
    Inventors: Madhusudhan Rangarajan, Nagasubramanian Gurumoorthy, Robert Cone, Rajesh Poornachandran, Kartik Ananthanarayanan, Rebecca Weekly
  • Publication number: 20190057000
    Abstract: Embodiments of the claimed invention include a computing device having a host processor for executing a firmware environment and a manageability controller. The firmware environment reserves a frame buffer in main memory and loads a graphics protocol driver to provide the frame buffer to an operating system of the computing device. The operating system renders graphical images to the frame buffer using a graphics driver. The manageability controller reads the graphical image from the frame buffer and may transmit the graphical image to a remote computing device. In response to a fatal error of the computing device, the manageability controller may store the graphical image to a non-volatile storage device. The host processor may assert a host reset signal in response to the fatal error, and the manageability controller may send an acknowledgment to the host processor after storing the graphical image. Other embodiments are described and claimed.
    Type: Application
    Filed: August 15, 2017
    Publication date: February 21, 2019
    Inventors: Kasper Wszolek, Janusz P. Jurski, Piotr Kwidzinski, Robert C. Swanson, Madhusudhan Rangarajan
  • Publication number: 20190044883
    Abstract: In multi-processor systems, some large jobs are performed by dividing the job into multiple tasks, having each task executed in parallel by separate nodes, and combining or synchronizing the results into a final answer. When communications between nodes represent a significant portion of total performance, techniques may be used to monitor and balance communications between the nodes so that the tasks will be completed at approximately the same time, thereby accelerating the completion of the job and avoiding wasting time and power by having some processors sit idle while waiting for other processors to catch up. Multiple synchronization points may be set up between the start and finish of task execution, to that mid-course corrections may be made.
    Type: Application
    Filed: January 11, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Janusz Piotr Jurski, Jonathan Eastep, Keith D. Underwood, Madhusudhan Rangarajan
  • Patent number: 10146657
    Abstract: Platform controller, computer-readable storage media, and methods associated with initialization of a computing device. In embodiments, a platform controller may comprise a boot controller and one or more non-volatile memory modules, coupled with the boot controller. In embodiments, the one or more non-volatile memory modules may have first instructions and second instructions stored thereon. The first instructions may, when executed by a processor of a computing device hosting the platform controller, cause initialization of the computing device. The second instructions, when executed by the boot controller, may cause the boot controller to monitor at least a portion of the execution of the first instructions by the computing device and may generate a trace of the monitored portion of the execution of the first instructions. In embodiments, the trace may be stored in the one or more non-volatile memory modules. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: December 4, 2018
    Assignee: Intel Corporation
    Inventors: Robert C. Swanson, C. Brendan Traw, Vincent J. Zimmer, Mallik Bulusu, John R. Lindsley, Mahesh S. Natu, Dimitrios Ziakas, Robert W. Cone, Madhusudhan Rangarajan, Babak Nikjou, Kirk D. Brannock, Russell J. Wunderlich, Miles F. Schwartz, Stephen S. Pawlowski
  • Patent number: 10073742
    Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Robert C. Swanson, Mariusz Oriol, Janusz Jurski, Piotr Sawicki, Robert W. Cone, William J. O'Sullivan, Mariusz Stepka, Babak Nikjou, Madhusudhan Rangarajan, Pawel Szymanski, Piotr Kwidzinski, Robert Bahnsen, Mallik Bulusu
  • Patent number: 9684457
    Abstract: Provided are a computer readable storage media, method, and system for gathering sensed data from devices to manage host command transmission and cooling of the device. Host commands are retrieved from a host memory in a host to perform Input/Output operations with respect to a device. The retrieved host commands are transmitted to the device to perform the I/O operations of the host command. A monitor command is transmitted to obtain sensed data from the device while processing the host commands. A rate of transmitting the host commands is adjusted in response to determining that the sensed data received from the device in response to the monitor command satisfies a condition.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: June 20, 2017
    Assignee: INTEL CORPORATION
    Inventors: Thanunathan Rangarajan, Eng Hun Ooi, Madhusudhan Rangarajan, Robert W. Cone, Nishi Ahuja
  • Publication number: 20170126619
    Abstract: A first computational device receives a response generated by a second computational device for a third computational device. A target that is suitable for use by the third computational device is determined. The response is transmitted with an address of the target to the third computational device.
    Type: Application
    Filed: January 12, 2017
    Publication date: May 4, 2017
    Inventors: Ramamurthy KRITHIVAS, Jacek RENIECKI, Daniel P. DALY, Madhusudhan RANGARAJAN
  • Patent number: 9577953
    Abstract: A first computational device receives a response generated by a second computational device for a third computational device. A target that is suitable for use by the third computational device is determined. The response is transmitted with an address of the target to the third computational device.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: February 21, 2017
    Assignee: INTEL CORPORATION
    Inventors: Ramamurthy Krithivas, Jacek Reniecki, Daniel P. Daly, Madhusudhan Rangarajan
  • Patent number: 9547497
    Abstract: Technologies for facilitating inter-system-on-a-chip (SoC) communication include a first SoC, a second SoC, and a dedicated manageability controller network. The first SoC includes a first main processor, a first manageability controller, and a memory dedicated to the first manageability controller and having manageability controller firmware stored thereon. The first manageability controller is different from the first main processor and to control functions of the first SoC. The second SoC is different from the first SoC and includes a second main processor and a second manageability control, which is different from the second main processor and to control functions of the second SoC. The second SoC is to access the manageability controller firmware of the memory of the first SoC over the dedicated manageability network.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: January 17, 2017
    Assignee: Intel Corporation
    Inventors: Robert C. Swanson, Robert W. Cone, William J. O'Sullivan, Mariusz Oriol, Pawel Szymanski, Babak Nikjou, Madhusudhan Rangarajan, Janusz Jurski, Piotr Kwidzinski, Mariusz Stepka, Piotr Sawicki
  • Publication number: 20160342328
    Abstract: Provided are a computer readable storage media, method, and system for gathering sensed data from devices to manage host command transmission and cooling of the device. Host commands are retrieved from a host memory in a host to perform Input/Output operations with respect to a device. The retrieved host commands are transmitted to the device to perform the I/O operations of the host command. A monitor command is transmitted to obtain sensed data from the device while processing the host commands. A rate of transmitting the host commands is adjusted in response to determining that the sensed data received from the device in response to the monitor command satisfies a condition.
    Type: Application
    Filed: May 21, 2015
    Publication date: November 24, 2016
    Inventors: Thanunathan RANGARAJAN, Eng Hun OOI, Madhusudhan RANGARAJAN, Robert W. CONE, Nishi AHUJA
  • Publication number: 20160292038
    Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.
    Type: Application
    Filed: June 9, 2016
    Publication date: October 6, 2016
    Inventors: Robert C. Swanson, Mariusz Oriol, Janusz Jurski, Piotr Sawicki, Robert W. Cone, William J. O'Sullivan, Mariusz Stepka, Babak Nikjou, Madhusudhan Rangarajan, Pawel Szymanski, Piotr Kwidzinski, Robert Bahnsen, Mallik Bulusu
  • Publication number: 20160202994
    Abstract: Technologies for facilitating inter-system-on-a-chip (SoC) communication include a first SoC, a second SoC, and a dedicated manageability controller network. The first SoC includes a first main processor, a first manageability controller, and a memory dedicated to the first manageability controller and having manageability controller firmware stored thereon. The first manageability controller is different from the first main processor and to control functions of the first SoC. The second SoC is different from the first SoC and includes a second main processor and a second manageability control, which is different from the second main processor and to control functions of the second SoC. The second SoC is to access the manageability controller firmware of the memory of the first SoC over the dedicated manageability network.
    Type: Application
    Filed: September 27, 2013
    Publication date: July 14, 2016
    Inventors: Robert C. SWANSON, Robert W. CONE, William J. O'SULLIVAN, Mariusz ORIOL, Pawel SZYMANSKI, BABAK NIKJOU, Madhusudhan RANGARAJAN, Janusz JURSKI, Piotr KWIDZINSKI, Mariusz STEPKA, Piotr SAWICKI
  • Patent number: 9367406
    Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: June 14, 2016
    Assignee: Intel Corporation
    Inventors: Robert C. Swanson, Mariusz Oriol, Janusz Jurski, Piotr Sawicki, Robert W. Cone, William J. O'Sullivan, Mariusz Stepka, Babak Nikjou, Madhusudhan Rangarajan, Pawel Szymanski, Piotr Kwidzinski, Robert Bahnsen, Mallik Bulusu
  • Patent number: 9183152
    Abstract: Before initializing a memory of an information handling system, a method includes loading an image of a video option ROM code for a graphics interface device to a cache associated with a processor of the information handling system, and executing the video option ROM code to initialize the graphics interface device. The method also includes executing a memory reference code to initialize the memory, and while executing the memory reference code, providing status information from the graphics interface device.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: November 10, 2015
    Assignee: Dell Products, LLP
    Inventors: Bi-Chong Wang, Austin P. Bolen, Madhusudhan Rangarajan
  • Publication number: 20150278068
    Abstract: Platform controller, computer-readable storage media, and methods associated with initialization of a computing device. In embodiments, a platform controller may comprise a boot controller and one or more non-volatile memory modules, coupled with the boot controller. In embodiments, the one or more non-volatile memory modules may have first instructions and second instructions stored thereon. The first instructions may, when executed by a processor of a computing device hosting the platform controller, cause initialization of the computing device. The second instructions, when executed by the boot controller, may cause the boot controller to monitor at least a portion of the execution of the first instructions by the computing device and may generate a trace of the monitored portion of the execution of the first instructions. In embodiments, the trace may be stored in the one or more non-volatile memory modules. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 1, 2015
    Inventors: Robert C. Swanson, C. Brendan Traw, Vincent J. Zimmer, Mallik Bulusu, John R. Lindsley, Mahesh S. Natu, Dimitrios Ziakas, Robert W. Cone, Madhusudhan Rangarajan, Babak Nikjou, Kirk D. Brannock, Russell J. Wunderlich, Miles F. Schwartz, Stephen S. Pawlowski
  • Patent number: 9110716
    Abstract: An information handling system includes a set of power and performance profiles. Based on which of the profiles has been selected, the information handling system selects a thread scheduling table for provision to an operating system. The thread scheduling table determines the sequence of processor cores at which program threads are scheduled for execution. In a power-savings mode, the corresponding thread scheduling table provides for threads to be concentrated at subset of available processor cores, increasing the frequency with which the information handling system can place unused processors in a reduced power state.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: August 18, 2015
    Assignee: Dell Products, LP
    Inventors: Mukund P. Khatri, Vijay Nijhawan, Dirie N. Herzi, Madhusudhan Rangarajan
  • Publication number: 20150095515
    Abstract: A first computational device receives a response generated by a second computational device for a third computational device. A target that is suitable for use by the third computational device is determined. The response is transmitted with an address of the target to the third computational device.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: Ramamurthy Krithivas, Jacek Reniecki, Daniel P. Daly, Madhusudhan Rangarajan
  • Publication number: 20150052389
    Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.
    Type: Application
    Filed: August 14, 2013
    Publication date: February 19, 2015
    Inventors: Robert C. Swanson, Mariusz Oriol, Janusz Jurski, Piotr Sawicki, Robert W. Cone, William J. O'Sullivan, Mariusz Stepka, Babak Nikjou, Madhusudhan Rangarajan, Pawel Szymanski, Piotr Kwidzinski, Robert Bahnsen, Mallik Bulusu
  • Publication number: 20150009225
    Abstract: Before initializing a memory of an information handling system, a method includes loading an image of a video option ROM code for a graphics interface device to a cache associated with a processor of the information handling system, and executing the video option ROM code to initialize the graphics interface device. The method also includes executing a. memory reference code to initialize the memory, and while executing the memory reference code, providing status information from the graphics interface device.
    Type: Application
    Filed: September 22, 2014
    Publication date: January 8, 2015
    Inventors: Bi-Chong Wang, Austin P. Bolen, Madhusudhan Rangarajan