Abstract: In one embodiment, a network switch includes multiple chips communicably coupled together and a buffered crossbar. Each chip is coupled to every other chip with two bi-directional serial channels and includes a slice of the buffered crossbar. One or more input ports, one or more output ports, and an input logic module are coupled to the plurality of chips, and the input logic module is configured to receive a packet of data, allocate the packet of data into one or more data fragments, and distribute the packet of data to the buffered crossbar. An output logic module is coupled to the chips and configured to retrieve the packet of data from the buffered crossbar, reconstruct the packet of data from the data fragments according to a gather scheme, and transmit the packet of data.

Abstract: In one embodiment, a network switch includes multiple chips communicably coupled together and a buffered crossbar. Each chip is coupled to every other chip with two bi-directional serial channels and includes a slice of the buffered crossbar. One or more input ports, one or more output ports, and an input logic module are coupled to the plurality of chips, and the input logic module is configured to receive a packet of data, allocate the packet of data into one or more data fragments, and distribute the packet of data to the buffered crossbar. An output logic module is coupled to the chips and configured to retrieve the packet of data from the buffered crossbar, reconstruct the packet of data from the data fragments according to a gather scheme, and transmit the packet of data.

Abstract: A data coding system that compresses data and enables data, e.g., prefix addresses, to be represented with significantly fewer memory cells when compared to conventional coding systems.

Abstract: A method of implementing classification CAM functionality using primarily RAM cells is disclosed. The method offers significantly more table entries in a given area, or significantly less area for a given table size than conventional ternary CAMs. The method is much more power-efficient, cheaper, and offers a greater range of features than conventional CAMs.

Abstract: A data coding system that compresses data and enables data, e.g., prefix addresses, to be represented with significantly fewer memory cells when compared to conventional coding systems.

Abstract: A method of implementing classification CAM functionality using primarily RAM cells is disclosed. The method offers significantly more table entries in a given area, or significantly less area for a given table size than conventional ternary CAMs. The method is much more power-efficient, cheaper, and offers a greater range of features than conventional CAMs.

Abstract: A method of implementing classification CAM functionality using primarily RAM cells is disclosed. The method offers significantly more table entries in a given area, or significantly less area for a given table size than conventional ternary CAMs. The method is much more power-efficient, cheaper, and offers a greater range of features than conventional CAMs.

Abstract: A data coding system that compresses data and enables data, e.g., prefix addresses, to be represented with significantly fewer memory cells when compared to conventional coding systems.

Abstract: A method of implementing classification CAM functionality using primarily RAM cells is disclosed.

Abstract: Circuits are described that can detect the presence or absence of an input number in a pre-defined list of numbers, and provide an index into the list for a matching number. The elements of the list of numbers may be individual numbers, or sets of numbers within a range of numbers.

Abstract: A data coding system that compresses data and enables data, e.g., prefix addresses, to be represented with significantly fewer memory cells when compared to conventional coding systems.

Abstract: A method of implementing classification CAM functionality using primarily RAM cells is disclosed. The method offers significantly more table entries in a given area, or significantly less area for a given table size than conventional ternary CAMs. The method is much more power-efficient, cheaper, and offers a greater range of features than conventional CAMs.

Abstract: A method of implementing classification CAM functionality using primarily RAM cells is disclosed. The method offers significantly more table entries in a given area, or significantly less area for a given table size than conventional ternary CAMs. The method is much more power-efficient, cheaper, and offers a greater range of features than conventional CAMs.

Abstract: A method of implementing classification CAM functionality using primarily RAM cells is disclosed. The method offers significantly more table entries in a given area, or significantly less area for a given table size than conventional ternary CAMs. The method is much more power-efficient, cheaper, and offers a greater range of features than conventional CAMs.

Abstract: A method of implementing classification CAM functionality using primarily RAM cells is disclosed. The method offers significantly more table entries in a given area, or significantly less area for a given table size than conventional ternary CAMs. The method is much more power-efficient, cheaper, and offers a greater range of features than conventional CAMs.

Abstract: A plurality of special multi-element registers, called "vector registers" herein, are incorporated into a scalar computer. The vector registers are controlled to sequence the transfer of vector data between a main memory and a processing unit of the computer to occur one element at a time until an entire array of vector data has been processed. The vector registers operate concurrently with the processing unit and the main memory. A common address scheme is used between the vector registers and the scalar registers of the computer so the vector registers are visible in the scalar register address space. Pointers are used in the vector registers to keep track of the order of the array elements during processing. Vector registers are used to store intermediate results of the vector processing operations.