Patents by Inventor Madjid Hafizi

Madjid Hafizi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5729033
    Abstract: A submicron emitter heterojunction bipolar transistor and a method for fabricating the same is disclosed. The fabrication process includes lattice matched growth of subcollector, collector, base, emitter, and emitter cap layers in sequential order on a semi-insulating semiconductor substrate. An emitter cap mesa, an emitter/base/collector mesa and a subcollector mesa are formed. Dielectric platforms are formed extending the base/collector layers laterally. Sidewalls are formed on the sides of emitter cap mesa and the sides of the extended base/collector layers and undercuts are etched into the emitter layer and the upper portion of the subcollector layer. This forms an overhang on the emitter cap mesa with respect to the emitter layer and an overhang on the base/collector layers with respect to the upper portion of the subcollector layer.
    Type: Grant
    Filed: October 31, 1996
    Date of Patent: March 17, 1998
    Assignee: Hughes Electronics
    Inventor: Madjid Hafizi
  • Patent number: 5665614
    Abstract: A submicron emitter heterojunction bipolar transistor and a method for fabricating the same is disclosed. The fabrication process includes lattice matched growth of subcollector, collector, base, emitter, and emitter cap layers in sequential order on a semi-insulating semiconductor substrate. An emitter cap mesa, an emitter/base/collector mesa and a subcollector mesa are formed. Dielectric platforms are formed extending the base/collector layers laterally. Sidewalls are formed on the sides of emitter cap mesa and the sides of the extended base/collector layers and undercuts are etched into the emitter layer and the upper portion of the subcollector layer. This forms an overhang on the emitter cap mesa with respect to the emitter layer and an overhang on the base/collector layers with respect to the upper portion of the subcollector layer.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: September 9, 1997
    Assignee: Hughes Electronics
    Inventors: Madjid Hafizi, William E. Stanchina
  • Patent number: 5468659
    Abstract: A photoresist process combined with wet chemical etching and silicon oxide evaporation and self-aligned lift-off is used to reduce the parasitic (extrinsic) base-collector junction capacitance (C.sub.BC) of InP-based heterojunction bipolar transistors (HBTs). At least a portion of the mesa related to the base contact is etched around the intrinsic device area and then back-filled with evaporated oxide. The base contact pad is then formed over the back-filled oxide, thus reducing the extrinsic device area. This process provides a self-aligned etching of a mesa and deposition and lift-off of the back-fill oxide in one single photoresist processing step. The process is simple and reproducible and provides very high yield. It also eliminates the need for costly and complicated dry-etching techniques.
    Type: Grant
    Filed: March 10, 1994
    Date of Patent: November 21, 1995
    Assignee: Hughes Aircraft Company
    Inventors: Madjid Hafizi, William E. Stanchina, William W. Hooper
  • Patent number: 5404028
    Abstract: An electrical junction is precisely located between a highly p doped semiconductor material and a more lightly n doped semiconductor material by providing a lightly p doped buffer region between the two materials, with a doping level on the order of the n doped material's. The buffer region is made wide enough to establish an electrical junction at approximately its interface with the n doped material, despite a diffusion of dopant from the p doped material. When applied to a heterojunction bipolar transistor (HBT), the transistor's base serves as the heavily p doped material and its emitter as the more lightly n doped material. The buffer region is preferably employed in conjunction with a graded superlattice, located between the buffer and emitter, which inhibits dopant diffusion from the base into the emitter.
    Type: Grant
    Filed: January 22, 1993
    Date of Patent: April 4, 1995
    Assignee: Hughes Aircraft Company
    Inventors: Robert A. Metzger, Madjid Hafizi, William E. Stanchina, David B. Rensch
  • Patent number: 5365077
    Abstract: A gain-stable npn heterojunction bipolar transistor includes a graded superlattice between its base and emitter consisting of multiple discrete periods, with each period having a layer of base material and another layer of emitter material. The thicknesses of the base material layers decrease while the thicknesses of the emitter material layers increase in discrete steps for each successive period from the base to the emitter. The thickness of each period is preferably at least about 20 Angstroms, with the superlattice including more than five periods. The superlattice is preferably doped to establish an electrical base-emitter junction at a desired location. The graded superlattice inhibits the diffusion of beryllium p dopant from the base into the emitter during transistor operation, thus stabilizing the device's gain and turn-on voltage.
    Type: Grant
    Filed: January 22, 1993
    Date of Patent: November 15, 1994
    Assignee: Hughes Aircraft Company
    Inventors: Robert A. Metzger, Madjid Hafizi, William E. Stanchina, Loren G. McCray