Patents by Inventor Madoka Nishikawa

Madoka Nishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11495248
    Abstract: A signal processing device includes a receiver that receives a plurality of playback signal sequence obtained by digitizing a plurality of reading results by a plurality of A/D converter, the plurality of reading results being obtained by reading data by a plurality of reading elements from a magnetic tape and a plurality of equalizers that perform waveform equalization of the plurality of playback signal sequence. The plurality of equalizers perform the waveform equalization by using a plurality of non-linear filters that have been learned to reduce distortion that occurs non-linearly in the plurality of playback signal sequence according to a condition under an environment in which the data is read from the magnetic tape. The plurality of non-linear filters being optimized to a suitable characteristic for the plurality of reading elements by optimization based on the plurality of reading results.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: November 8, 2022
    Assignee: FUJIFILM Corporation
    Inventors: Atsushi Musha, Yoshihiro Okamoto, Yasuaki Nakamura, Madoka Nishikawa
  • Publication number: 20210398554
    Abstract: A signal processing device includes a receiver that receives a plurality of playback signal sequence obtained by digitizing a plurality of reading results by a plurality of A/D converter, the plurality of reading results being obtained by reading data by a plurality of reading elements from a magnetic tape and a plurality of equalizers that perform waveform equalization of the plurality of playback signal sequence. The plurality of equalizers perform the waveform equalization by using a plurality of non-linear filters that have been learned to reduce distortion that occurs non-linearly in the plurality of playback signal sequence according to a condition under an environment in which the data is read from the magnetic tape. The plurality of non-linear filters being optimized to a suitable characteristic for the plurality of reading elements by optimization based on the plurality of reading results.
    Type: Application
    Filed: June 22, 2021
    Publication date: December 23, 2021
    Applicant: FUJIFILM Corporation
    Inventors: Atsushi MUSHA, Yoshihiro OKAMOTO, Yasuaki NAKAMURA, Madoka NISHIKAWA
  • Patent number: 7855902
    Abstract: In a DC-DC converter of this invention, a voltage detection circuit is connected in parallel with an output switching device, and the voltage detection circuit is put into operation a predetermined time after the output switching device is turned on. In addition, a detection switching device, which constitutes the voltage detection circuit, is designed to have a higher ON resistance than an ON resistance of the output switching device.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: December 21, 2010
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Yukio Goto, Madoka Nishikawa
  • Publication number: 20080116864
    Abstract: A detection resistor is disposed in a main current path in order to detect an output current flowing through an output switching device in a conventional DC-DC converter that converts a DC input voltage into a stepped down DC output voltage by turning on/off of the output switching device. At that time, the detection resistor generates heat that is not negligible. In a DC-DC converter of this invention, a voltage detection circuit is connected in parallel with an output switching device, and the voltage detection circuit is put into operation a predetermined time after the output switching device is turned on. In addition, a detection switching device, which constitutes the voltage detection circuit, is designed to have a higher ON resistance than an ON resistance of the output switching device.
    Type: Application
    Filed: October 24, 2007
    Publication date: May 22, 2008
    Inventors: Yukio Goto, Madoka Nishikawa
  • Patent number: 6861732
    Abstract: In a conventional power circuit device, such as a power MOSFET monolithic integrated circuit device and a compound device, since five lead pins are lead out from the packaging with even intervals, sufficient separation distances between the third pin of a high voltage and other adjacent pins cannot be secured. According to this invention, the distances between the third pin and other adjacent pins are expanded so as to become wider than the distances between other pins. Furthermore, the third pin is formed into an upper position, its adjacent pins are formed into a lower position, and other pins are formed into a middle position. Thereby, sufficient separation distances between the third pin of the high voltage and other adjacent pins can be secured. Therefore, a structure favorable in terms of safety can be provided. Furthermore, by providing a full-mold packaging, the header portion is not exposed to assure an easy handling.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: March 1, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Mitsuho Tsuchida, Madoka Nishikawa, Kenji Ikeda