Abstract: A solid-state non-volatile memory (NVM) device includes a memory bit cell. The memory bit cell includes a field effect transistor (FET) fabricated on a substrate and having a floating gate. The floating gate includes a thick oxide layer. The FET includes drain and source, each fabricated within the substrate and coupled to the floating gate and a channel region with native doping. The drain is fabricated to have a halo region. A method for fabricating a solid-state NVM device includes fabricating solid state device including NVM bit cell which provides multiple storage and includes an FET on substrate. The method also includes fabricating floating gate of the FET including thick gate oxide layer, and fabricating drain and source of FET within the substrate, drain and source coupled to the floating gate and channel region with native doping. Further, the method includes fabricating halo region within the substrate at the drain.

Abstract: A solid-state non-volatile memory (NVM) device includes a memory bit cell. The memory bit cell includes a field effect transistor (FET) fabricated on a substrate and having a floating gate. The floating gate includes a thick oxide layer. The FET includes drain and source, each fabricated within the substrate and coupled to the floating gate and a channel region with native doping. The drain is fabricated to have a halo region. A method for fabricating a solid-state NVM device includes fabricating solid state device including NVM bit cell which provides multiple storage and includes an FET on substrate. The method also includes fabricating floating gate of the FET including thick gate oxide layer, and fabricating drain and source of FET within the substrate, drain and source coupled to the floating gate and channel region with native doping. Further, the method includes fabricating halo region within the substrate at the drain.