Patents by Inventor Magali Gregoire
Magali Gregoire has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230326947Abstract: An integrated circuit includes at least one silicon region and at least one metal pillar in contact with the at least one silicon region at an ohmic coupling region. The at least one metal pillar is formed by: depositing a layer of titanium on the at least one silicon region; depositing atomic layers of titanium nitride on the layer of titanium; and annealing at a temperature of between 715° C. and 815° C. for a period of between 5 seconds and 30 seconds. This forms a titanium silicide for the ohmic coupling region in a volume having the appearance of a spherical cap or segment.Type: ApplicationFiled: April 6, 2023Publication date: October 12, 2023Applicant: STMicroelectronics (Crolles 2) SASInventors: Magali GREGOIRE, Joel SCHMITT
-
Publication number: 20230170260Abstract: An integrated circuit includes first semiconductor regions each having a silicided portion with group-III, group-IV, and/or group-V atoms implanted therein. In each first semiconductor region, a concentration of the group-III, group-IV, and/or group-V atoms is maximum at an interface between the silicided portion and a non-silicided portion. Other semiconductor regions in the integrated circuit each include a silicided portion also having group-III, group-IV, and/or group-V atoms implanted therein. The silicided portions of the first semiconductor regions are thicker than the silicided portions of the other semiconductor regions. The group-III, group-IV, and/or group-V atoms of the first semiconductor regions and of the other semiconductor regions may be carbon and/or germanium atoms.Type: ApplicationFiled: January 27, 2023Publication date: June 1, 2023Applicant: STMicroelectronics (Crolles 2) SASInventor: Magali GREGOIRE
-
Patent number: 11610813Abstract: An interconnection element of an interconnection structure of an integrated circuit is manufactures by a method where a cavity is etched in an insulating layer. A silicon nitride layer is then deposited on walls and a bottom of the cavity. The nitrogen atom concentration in the silicon nitride layer increasing as a distance from an exposed surface of the silicon nitride layer increases. A copper layer is deposited on the silicon nitride layer. The cavity is further filled with copper. A heating process is performed after the deposition of the copper layer, to convert the copper layer and the silicon nitride layer to form a copper silicide layer which has a nitrogen atom concentration gradient corresponding to the gradient of the silicon nitride layer.Type: GrantFiled: September 29, 2021Date of Patent: March 21, 2023Assignee: STMicroelectronics (Crolles 2) SASInventor: Magali Gregoire
-
Patent number: 11322363Abstract: Atoms are implanted in a semiconductor region at a higher concentration in a peripheral part of the semiconductor region than in a central part of the semiconductor region. A metallic region is then formed to cover the semiconductor region. A heat treatment is the performed to form an intermetallic region from the metallic region and the semiconductor region.Type: GrantFiled: June 4, 2020Date of Patent: May 3, 2022Assignee: STMicroelectronics (Crolles 2) SASInventors: Julien Borrel, Magali Gregoire
-
Publication number: 20220020640Abstract: An interconnection element of an interconnection structure of an integrated circuit is manufactures by a method where a cavity is etched in an insulating layer. A silicon nitride layer is then deposited on walls and a bottom of the cavity. The nitrogen atom concentration in the silicon nitride layer increasing as a distance from an exposed surface of the silicon nitride layer increases. A copper layer is deposited on the silicon nitride layer. The cavity is further filled with copper. A heating process is performed after the deposition of the copper layer, to convert the copper layer and the silicon nitride layer to form a copper silicide layer which has a nitrogen atom concentration gradient corresponding to the gradient of the silicon nitride layer.Type: ApplicationFiled: September 29, 2021Publication date: January 20, 2022Applicant: STMicroelectronics (Crolles 2) SASInventor: Magali GREGOIRE
-
Patent number: 11222957Abstract: A NiPt layer with a Pt atom concentration equal to 15% plus or minus 1% is deposited on a semiconductor region (which may, for example, be a source/drain region of a MOS transistor). An anneal is then performed at a temperature of 260° C. plus or minus 20° C., for a duration in the range from 20 to 60 seconds, in order to produce, from the Nickle-Platinum (NiPt) layer and the semiconductor material of said semiconductor region, an intermetallic layer. Advantageously, the intermetallic layer possesses a structure of heteroepitaxy with the semiconductor material, and includes free Pt atoms.Type: GrantFiled: June 22, 2020Date of Patent: January 11, 2022Assignee: STMicroelectronics (Crolles 2) SASInventor: Magali Gregoire
-
Patent number: 11152259Abstract: An interconnection element of an interconnection structure of an integrated circuit is manufactures by a method where a cavity is etched in an insulating layer. A silicon nitride layer is then deposited on walls and a bottom of the cavity. The nitrogen atom concentration in the silicon nitride layer increasing as a distance from an exposed surface of the silicon nitride layer increases. A copper layer is deposited on the silicon nitride layer. The cavity is further filled with copper. A heating process is performed after the deposition of the copper layer, to convert the copper layer and the silicon nitride layer to form a copper silicide layer which has a nitrogen atom concentration gradient corresponding to the gradient of the silicon nitride layer.Type: GrantFiled: May 22, 2020Date of Patent: October 19, 2021Assignee: STMicroelectronics (Crolles 2) SASInventor: Magali Gregoire
-
Publication number: 20200411657Abstract: A NiPt layer with a Pt atom concentration equal to 15% plus or minus 1% is deposited on a semiconductor region (which may, for example, be a source/drain region of a MOS transistor). An anneal is then performed at a temperature of 260° C. plus or minus 20° C., for a duration in the range from 20 to 60 seconds, in order to produce, from the Nickle-Platinum (NiPt) layer and the semiconductor material of said semiconductor region, an intermetallic layer. Advantageously, the intermetallic layer possesses a structure of heteroepitaxy with the semiconductor material, and includes free Pt atoms.Type: ApplicationFiled: June 22, 2020Publication date: December 31, 2020Applicant: STMicroelectronics (Crolles 2) SASInventor: Magali GREGOIRE
-
Publication number: 20200388505Abstract: Atoms are implanted in a semiconductor region at a higher concentration in a peripheral part of the semiconductor region than in a central part of the semiconductor region. A metallic region is then formed to cover the semiconductor region. A heat treatment is the performed to form an intermetallic region from the metallic region and the semiconductor region.Type: ApplicationFiled: June 4, 2020Publication date: December 10, 2020Applicant: STMicroelectronics (Crolles 2) SASInventors: Julien BORREL, Magali GREGOIRE
-
Publication number: 20200381297Abstract: An interconnection element of an interconnection structure of an integrated circuit is manufactures by a method where a cavity is etched in an insulating layer. A silicon nitride layer is then deposited on walls and a bottom of the cavity. The nitrogen atom concentration in the silicon nitride layer increasing as a distance from an exposed surface of the silicon nitride layer increases. A copper layer is deposited on the silicon nitride layer. The cavity is further filled with copper. A heating process is performed after the deposition of the copper layer, to convert the copper layer and the silicon nitride layer to form a copper silicide layer which has a nitrogen atom concentration gradient corresponding to the gradient of the silicon nitride layer.Type: ApplicationFiled: May 22, 2020Publication date: December 3, 2020Applicant: STMicroelectronics (Crolles 2) SASInventor: Magali GREGOIRE
-
Publication number: 20190363021Abstract: An integrated circuit includes first semiconductor regions each having a silicided portion with group-III, group-IV, and/or group-V atoms implanted therein. In each first semiconductor region, a concentration of the group-III, group-IV, and/or group-V atoms is maximum at an interface between the silicided portion and a non-silicided portion. Other semiconductor regions in the integrated circuit each include a silicided portion also having group-III, group-IV, and/or group-V atoms implanted therein. The silicided portions of the first semiconductor regions are thicker than the silicided portions of the other semiconductor regions. The group-III, group-IV, and/or group-V atoms of the first semiconductor regions and of the other semiconductor regions may be carbon and/or germanium atoms.Type: ApplicationFiled: May 15, 2019Publication date: November 28, 2019Applicant: STMicroelectronics (Crolles 2) SASInventor: Magali GREGOIRE
-
Patent number: 9257291Abstract: A method for manufacturing a silicide layer in a hole formed across the entire thickness of a layer of a material deposited on a silicon layer, including: a first step of bombarding of the hole with particles to sputter the silicon at the bottom of the hole and deposit sputtered silicon on lateral walls of the hole; a second step of deposition in the hole of a layer of silicide precursor; a second step of bombarding of the hole with particles to sputter the silicon precursor at the bottom of the hole and deposit sputtered precursor on the internal walls of the hole; a second step of deposition in the hole of a layer of silicide precursor; and an anneal step to form a silicide layer in the hole.Type: GrantFiled: September 7, 2012Date of Patent: February 9, 2016Assignee: STMicroelectronics (Crolles 2) SASInventor: Magali Gregoire
-
Publication number: 20130065392Abstract: A method for manufacturing a silicide layer in a hole formed across the entire thickness of a layer of a material deposited on a silicon layer, including: a first step of bombarding of the hole with particles to sputter the silicon at the bottom of the hole and deposit sputtered silicon on lateral walls of the hole; a second step of deposition in the hole of a layer of silicide precursor; a second step of bombarding of the hole with particles to sputter the silicon precursor at the bottom of the hole and deposit sputtered precursor on the internal walls of the hole; a second step of deposition in the hole of a layer of silicide precursor; and an anneal step to form a silicide layer in the hole.Type: ApplicationFiled: September 7, 2012Publication date: March 14, 2013Applicant: STMICROELECTRONICS (CROLLES 2) SASInventor: Magali Gregoire
-
Patent number: 7531447Abstract: An integrated circuit includes copper lines, wherein the crystal structure of the copper has a greater than 30% <001 > crystal orientation and a less than 20% <111> crystal orientation.Type: GrantFiled: September 6, 2005Date of Patent: May 12, 2009Assignee: STMicroelectronics SAInventors: Pierre Caubet, Magali Gregoire
-
Publication number: 20060060976Abstract: An integrated circuit includes copper lines, wherein the crystal structure of the copper has a greater than 30% <001 > crystal orientation and a less than 20% <111> crystal orientation.Type: ApplicationFiled: September 6, 2005Publication date: March 23, 2006Applicant: STMICROELECTRONICS SAInventors: Pierre Caubet, Magali Gregoire