Patents by Inventor Magali Gregoire

Magali Gregoire has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190363021
    Abstract: An integrated circuit includes first semiconductor regions each having a silicided portion with group-III, group-IV, and/or group-V atoms implanted therein. In each first semiconductor region, a concentration of the group-III, group-IV, and/or group-V atoms is maximum at an interface between the silicided portion and a non-silicided portion. Other semiconductor regions in the integrated circuit each include a silicided portion also having group-III, group-IV, and/or group-V atoms implanted therein. The silicided portions of the first semiconductor regions are thicker than the silicided portions of the other semiconductor regions. The group-III, group-IV, and/or group-V atoms of the first semiconductor regions and of the other semiconductor regions may be carbon and/or germanium atoms.
    Type: Application
    Filed: May 15, 2019
    Publication date: November 28, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Magali GREGOIRE
  • Patent number: 9257291
    Abstract: A method for manufacturing a silicide layer in a hole formed across the entire thickness of a layer of a material deposited on a silicon layer, including: a first step of bombarding of the hole with particles to sputter the silicon at the bottom of the hole and deposit sputtered silicon on lateral walls of the hole; a second step of deposition in the hole of a layer of silicide precursor; a second step of bombarding of the hole with particles to sputter the silicon precursor at the bottom of the hole and deposit sputtered precursor on the internal walls of the hole; a second step of deposition in the hole of a layer of silicide precursor; and an anneal step to form a silicide layer in the hole.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: February 9, 2016
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Magali Gregoire
  • Publication number: 20130065392
    Abstract: A method for manufacturing a silicide layer in a hole formed across the entire thickness of a layer of a material deposited on a silicon layer, including: a first step of bombarding of the hole with particles to sputter the silicon at the bottom of the hole and deposit sputtered silicon on lateral walls of the hole; a second step of deposition in the hole of a layer of silicide precursor; a second step of bombarding of the hole with particles to sputter the silicon precursor at the bottom of the hole and deposit sputtered precursor on the internal walls of the hole; a second step of deposition in the hole of a layer of silicide precursor; and an anneal step to form a silicide layer in the hole.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 14, 2013
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventor: Magali Gregoire
  • Patent number: 7531447
    Abstract: An integrated circuit includes copper lines, wherein the crystal structure of the copper has a greater than 30% <001 > crystal orientation and a less than 20% <111> crystal orientation.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: May 12, 2009
    Assignee: STMicroelectronics SA
    Inventors: Pierre Caubet, Magali Gregoire
  • Publication number: 20060060976
    Abstract: An integrated circuit includes copper lines, wherein the crystal structure of the copper has a greater than 30% <001 > crystal orientation and a less than 20% <111> crystal orientation.
    Type: Application
    Filed: September 6, 2005
    Publication date: March 23, 2006
    Applicant: STMICROELECTRONICS SA
    Inventors: Pierre Caubet, Magali Gregoire