Patents by Inventor Maganlal S. Patel

Maganlal S. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5604445
    Abstract: An apparatus, and a corresponding method, for stress testing both wire bond-type semiconductor chips and C4-type semiconductor chips is disclosed.
    Type: Grant
    Filed: December 21, 1994
    Date of Patent: February 18, 1997
    Assignee: International Business Machines Corporation
    Inventors: Kishor V. Desai, Maganlal S. Patel, Sanjeev Sathe
  • Patent number: 5263245
    Abstract: An electronic package which includes a substrate having a dielectric layer, a circuitized layer located on one surface of the dielectric and a thermally and electrically conductive layer located on a second surface of the dielectric, this thermally and conductive layer designed for providing enhanced heat removal from the package's semiconductor device. A pedestal element is located on or formed as part of the thermal and electrically conductive layer, and extends through the dielectric and circuitized layers for having the semiconductor device positioned thereon. The semiconductor device is thus in substantially direct thermal communication with the pedestal element and thus the adjacent, thick thermal conductive layer which functions as the package's heat sink. In one embodiment, solder is provided on the pedestal element to interconnect desired portions of the circuitized layer with the pedestal element (e.g., to provide electrical ground).
    Type: Grant
    Filed: February 16, 1993
    Date of Patent: November 23, 1993
    Assignee: International Business Machines Corporation
    Inventors: Maganlal S. Patel, John J. Zopff
  • Patent number: 5220487
    Abstract: An electronic package which includes a substrate having a dielectric layer, a circuitized layer located on one surface of the dielectric and a thermally and electrically conductive layer located on a second surface of the dielectric, this thermally and conductive layer designed for providing enhanced heat removal from the package's semiconductor device. A pedestal element is located on or formed as part of the thermal and electrically conductive layer, and extends through the dielectric and circuitized layers for having the semiconductor device positioned thereon. The semiconductor device is thus in substantially direct thermal communication with the pedestal element and thus the adjacent, thick thermal conductive layer which functions as the package's heat sink. In one embodiment, solder is provided on the pedestal element to interconnect desired portions of the circuitized layer with the pedestal element (e.g., to provide electrical ground).
    Type: Grant
    Filed: January 27, 1992
    Date of Patent: June 15, 1993
    Assignee: International Business Machines Corporation
    Inventors: Maganlal S. Patel, John J. Zopff
  • Patent number: 5137456
    Abstract: An electrical connector for interconnecting a pair of circuit members (e.g., printed circuit boards) wherein the connector includes a plurality of electrical contacts, these contacts including at least one semi-spherical end portion for engaging a respective conductor on one of the circuit members. Significantly, the semi-spherical end portion is capable of moving in two different directions of rotation during such engagement to provide an effective wiping motion against the surfaces of the member's conductor. In one embodiment, the connector includes contacts with opposed, semi-spherical end portions, while in another embodiment, a singular semi-spherical end portion is taught.
    Type: Grant
    Filed: November 4, 1991
    Date of Patent: August 11, 1992
    Assignee: International Business Machines Corporation
    Inventors: Kishor V. Desai, Thomas G. Macek, Maganlal S. Patel, Edwin L. Thomas