Abstract: A direct digital synthesizer (DDS) is controlled by a suitably configured programmable logic device (PLD). The DDS includes a digital analog converter (DAC), and a coupled driver/buffer configured to drive relatively high capacitive loads with substantially rail to rail sinusoidal driver output signals and with little to no waveform distortion. The DAC includes a PMOS and NMOS DACs, and a switch configured to select the PMOS DAC for negative portions and the NMOS DAC for positive portions of an output analog signal generated by the DAC. The driver includes a pair of input differential amplifiers, PMOS and NMOS structures, which may be variable, and a pair of variable current sources. The PLD controls variable elements of the DDS to adjust the achievable positive and negative slew rates of the DDS, independently of one another, to reduce or eliminate risk of signal distortion while maintaining substantially stable rail to rail output.

Abstract: Systems and methods for direct digital synthesis are disclosed. A direct digital synthesis system includes a direct digital synthesizer (DDS) and a programmable logic device (PLD) configured to control the DDS. The DDS includes at least one digital analog converter (DAC) and a coupled driver/buffer configured to drive relatively high capacitive loads with substantially rail to rail sinusoidal driver output signals and with little to no waveform distortion. The DAC includes a PMOS DAC and an NMOS DAC and a switch configured to select the PMOS DAC for negative portions and the NMOS DAC for positive portions of an output analog signal generated by the DAC. The driver includes a pair of input differential amplifiers, PMOS and NMOS transistor structures, which may be variable, and a pair of variable current sources.

Abstract: In one embodiment, an integrated circuit has one or more multi-channel transmitters, each transmitter having synchronization circuitry that synchronizes different copies of a reset signal used to reset different sets of TX channel circuitry used to generate the multiple TX signals, to reduce the skew between the different TX signals. Each set of synchronization circuitry has (at least) two synchronization stages that re-time different copies of the reset signal to a selected clock signal. In one implementation, the integrated circuit has (at least) two quads, each of which can generate four different TX signals, where both quads can be configured to use the same clock signal to re-time different copies of the reset signal such that the eight different TX signals are all synchronized to one another.

Abstract: In one embodiment, a voltage-controlled oscillator has a ring of delay stages and power-regulating circuitry regulating power to each delay stage. Each delay stage has at least one inverter having a leg having a current regulator that controls current flowing through the leg and thereby controlling gain of the delay stage. The VCO receives three control signals that affect the amount of delay applied by each delay stage and therefore the VCO output frequency: a first applied to control the power-regulating circuitry, a second applied to at least one transistor gate in the current regulator, and a third applied to at least one transistor body in the current regulator. The power-regulating circuitry has a parallel configuration of a power-regulating transistor, a first capacitor, and a switched-capacitor leg having a second capacitor and a switch for controlling settling time. The capacitors regulate the power supply without a dedicated, opamp-based voltage regulator.

Abstract: In an integrated circuit, meta-stability prevention circuitry prevents an oscillator, such as a current-controlled oscillator having a ring of differential inverters, from being turned on, for example, during power up, until after the power-supply voltage is sufficiently high for the oscillator ring to achieve oscillation without going into a meta-stable state. In one implementation, a level detector monitors the power-supply voltage level and generates a logic signal indicating whether or not the power-supply voltage level is sufficiently high. That logic signal and a conventional chip-level power-down control signal are applied to logic circuitry that generates control signals for one or more switch transistors that selectively turn on and off the oscillator ring.

Abstract: In several embodiments of the invention, a programmable architecture for FIR filters includes a tapped delay chain and a number of different slices. Each slice has a multiplexer that receives all of the tapped input-signal samples and a programmable current driver. Each slice can be independently programmed to correspond to any one of the taps in the delay chain, such that zero, one, or more slices can be associated with any of the delay-chain taps. Moreover, the current driver in each slice can be independently programmed to contribute any available driver strength level for the selected tap, where the combination of one or more drive strengths associated with a given tap corresponds to the effective tap coefficient for that tap. In this way, the architecture can be programmed to provide a variety of different filters having not just transfer functions with different coefficient values, but also transfer functions having different numbers of pre-cursor and/or post-cursor taps.

Abstract: In one embodiment, a hybrid output buffer having both an H-bridge mode and a CML mode of operation includes a plurality of transistor switches arranged between an upper rail and a bottom rail. A first pair of the transistor switches couples between the upper rail and respective output nodes. A pair of resistors couples between the output nodes and a central node. During H-bridge mode, the hybrid output buffer controls a potential of the upper rail responsive to a feedback signal proportional to a difference between a potential of the central node and a common-mode voltage.