Abstract: A method of controlling asymmetrical port access in a common-memory (CM) multi-port data packet switch and a high-capacity flexible access rate CM data packet switch are described. The method involves providing a common-memory-access control table which defines a unique contiguous band of CM access time slots allocated to each port of the packet switch. Each access time slot is identified by a time slot identifier. Time slot identifiers are generated at a regular interval. The time slot identifiers are generated so that CM access time for each port is substantially equally spaced to minimize delay jitter. The packet switch may have an equal number of input and output ports, or more output ports than input ports. In the high-capacity CM packet switch, several CM switch modules are interlinked by middle buffers in a folded configuration to provide a packet switch having Terabit output capacity.

Abstract: Techniques of service-rate controls in ATM switches are described, and apparatus for their implementation are devised. The techniques fall in two categories: frequency domain controls, and time-domain controls. The regulators control the service rate on a per-class basis or on a per-connection basis. Some class regulators operate at very high speeds of the order of several gigabits per second and cover a medium number of classes, 32 for example. Other regulators operate at high speeds of the order of several-hundred megabits per second, and cover a very large number of classes, e.g., 10000. A compound regulator which combines both types of regulators is also described. The compound regulators extend the range of controllable classes considerably, covering some 200,000 classes. The main advantages of the regulators of the invention are simplicity, robustness, and high performance.

Abstract: Techniques of service-rate controls in ATM switches are described, and apparatus for their implementation are devised. The techniques fall in two categories: frequency domain controls, and time-domain controls. The regulators control the service rate on a per-class basis or on a per-connection basis. Some class regulators operate at very high speeds of the order of several gigabits per second and cover a medium number of classes, 32 for example. Other regulators operate at high speeds of the order of several-hundred megabits per second, and cover a very large number of classes, e.g., 10000. A compound regulator which combines both types of regulators is also described. The compound regulators extend the range of controllable classes considerably, covering some 200,000 classes. The main advantages of the regulators of the invention are simplicity, robustness, and high performance.

Abstract: A method for scheduling low delay-jitter cell transmissions for multiple streams of Asynchronous Transfer Mode (ATM) traffic from a node is disclosed. Cells belonging to multiple streams of virtual circuits (VCs) and virtual paths (VPs) are stored in the node's memory. A link controller scans a time-space map to determine when a given stream will be sampled and its cells transmitted from the memory out over a link. The time-space map is comprised of time-slots whose spatial positions within the map correspond to times at which cells can be transmitted. A scattering technique, based on reverse-binary or other mapping schemes, ensures that each given stream occupies time-slots that are well-spaced within the time-space map. This ensures that cells belonging to a given stream are transmitted at well-spaced intervals of time.

Abstract: A multi-stage ATM switch has a plurality of inlet stage fabrics, core stage fabrics and outlet stage fabrics. ATM cells routed by the switch have destination fields including (i) an identification of the outlet stage fabric and (ii) an identification of the outlet port. Cells incoming to a given inlet stage fabric are queued up in queues representing each of the outlet stage fabrics. A queue having at least the number of cells as there are core stage fabrics (or one having a lesser number of cells where cells have been waiting longer than an a pre-defined time) is identified and, in a time slot, cells are transmitted from the front of the identified queue, in parallel, one to each of the core stage fabrics (with blank make-up cells being sent, as necessary, where the identified queue had less cells than there are core stage fabrics).

Abstract: The invention resides in a precise technique for determining the equivalent bit rate (EBR) of a variable bit rate (VBR) ATM connection. The technique extends a known single-source method developed by Gibbens and Hunt. The new technique applies to shared facilities and hence exploits the statistical-multiplexing gain. The calculation of the EBR is quite fast and is therefore suitable for real-time call-admission control in ATM switches. The admission criteria may be based on either the cell loss or cell delay.

Abstract: An ATM switch architecture expandable to multi-terabits/s uses data transfer in a heterogeneous burst of a constant length. It employs rotators connecting stages in a three-stage switch configuration. In one embodiment, the cells are sorted at ingress and a matching process is performed between the first and middle stages. The switch is simple to control and has high performance at both the call and cell levels. It also meets the basic requirements that cells be delivered in the proper order, and that the rate of any individual connection be as high as the inlet-port rate. With a small internal expansion, the switch is non-blocking in the sense that any bit-rate acceptable to both the inlet and outlet ports will be guaranteed a path through the core. This feature is particularly useful in services which may require frequent bit-rate change during the connection time.

Abstract: A routing scheme for an ATM switching network includes a plurality of switching nodes, each of which includes individual storage for storing routing messages for each outgoing link. A call at a source node is routed through one possible routing path which requires only one or two links to complete a connection to a destination node. In such case, one of the routing paths is selected based on link state information concerning only the possible routing paths. If the call requires a route path which includes three or more links to the destination node, the source node performs a predefined sequential routing to its neighboring node before the neighboring node negotiates with selected intermediate nodes for a connection involving two links. The routing messages stored at each node are processed independently and simultaneously by each node. The main requirement is that routing decisions must be based on true link-state information.

Abstract: A new architecture of an ATM or ATM/STM switching node which is functionally equivalent to the classical buffer-space-buffer (BSB) architecture is disclosed. In the basic embodiment, it uses middle packet buffers with a rotator (commutator) at its input and output. It has two main advantages over the BSB architecture. First of all, in the ATM mode, the need for arbitration when more than one inlet competes for the same outlet during the same time slot is eliminated. Each packet knows when to proceed without being aware of the competing packets. This greatly simplifies the switching-control mechanism. Secondary, the switch hardware complexity is reduced through the use of clock-driven rather than state-controlled cross points. The cross-point ratio is 4/.sqroot.n, where n is the number of inlets (outlets).

Abstract: A synchronous time division multiplexing system for multi-channel calls involves dividing each frame into a first segment and a second segment each containing substantially the same number of time slots and dividing the number of channels of the multi-channel call into a first subset and a second subset each containing approximately the same number of channels. Thereafter, the first subset is assigned to the first segment of the first frame and the second subset to the second segment of the first frame. The invention involves in a first time switching stage transposing the first subset to the second segment of the first frame such that the channels within the first subset occupy eligible free slots and retain their relative order and transposing the second subset to the first segment of the next frame such that the channels within the second subset occupy eligible free slots and retain their relative order. The call subsets are thus transported during a single stage of time switching.