Patents by Inventor Maged Ghoneima

Maged Ghoneima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low power serial link bus architecture
    Patent number: 7817068
    Abstract: Embodiments of the present invention provide a bus architecture utilizing multiple-pumped serial links, and a combination of encoding and serialization to two data streams to transmit and receive a serialized data stream over a bus. The order in which encoding and serialization takes place depends upon the anticipated activity factors of the two data streams, and is chosen to reduce average energy dissipation. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: October 19, 2010
    Assignee: Intel Corporation
    Inventors: Maged Ghoneima, Muhammad M. Khellah, Vivek K. De
  • LOW POWER SERIAL LINK BUS ARCHITECTURE
    Publication number: 20080001793
    Abstract: Embodiments of the present invention provide a bus architecture utilizing multiple-pumped serial links, and a combination of encoding and serialization to two data streams to transmit and receive a serialized data stream over a bus. The order in which encoding and serialization takes place depends upon the anticipated activity factors of the two data streams, and is chosen to reduce average energy dissipation. Other embodiments are described and claimed.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Maged Ghoneima, Muhammad M. Khellah, Vivek K. De
  • Single-stage and multi-stage low power interconnect architectures
    Publication number: 20060109028
    Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.
    Type: Application
    Filed: December 22, 2005
    Publication date: May 25, 2006
    Inventors: Maged Ghoneima, Peter Caputa, Muhammad Khellah, Ram Krishnamurthy, James Tschanz, Yibin Ye, Vivek De, Yehia Ismail
  • Interconnect structure in integrated circuits
    Publication number: 20060001103
    Abstract: A device includes an interconnect structure having a number of circuit paths to transfer signals. The circuit paths transfer the signals at different speed to reduce the coupling capacitance effect between adjacent circuit paths.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventors: Maged Ghoneima, Muhammad Khellah, James Tschanz, Yibin Ye, Vivek De
  • Single-stage and multi-stage low power interconnect architectures
    Publication number: 20050225459
    Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 13, 2005
    Inventors: Maged Ghoneima, Peter Caputa, Muhammad Khellah, Ram Krishnamurthy, James Tschanz, Yibin Ye, Vivek De, Yehea Ismail