Abstract: In at least some embodiments, a processor core executes a code segment including a memory transaction and a non-transactional memory access instructions preceding the memory transaction in program order. The memory transaction includes at least an initiating instruction, a transactional memory access instruction, and a terminating instruction. The initiating instruction has an implicit barrier that imparts the effect of ordering execution of the transactional memory access instruction within the memory transaction with respect to the non-transactional memory access instructions preceding the memory transaction in program order. Executing the code segment includes executing the transactional memory access instruction within the memory transaction concurrently with at least one of the non-transactional memory access instructions preceding the memory transaction in program order and enforcing the barrier implicit in the initiating instruction following execution of the initiating instruction.

Abstract: A transactional memory system controls the coalescing of outermost memory transactions. The coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. A processor of the transactional memory system executes a run-time instrumentation program for monitoring and modifying an associated program having a plurality of transactions. Based, at least in part, on an analysis of gathered instrumentation information, the processor dynamically modifies continued execution of the plurality of transactions by adding a coalescing instruction that controls, at least in part, a coalescing of one or more outermost transactions of the plurality of transactions.

Abstract: Discontiguous storage locations are prefetched by a prefetch instruction. Addresses of the discontiguous storage locations are provided by a list directly or indirectly specified by a parameter of the prefetch instruction, along with metadata and information about the list entries. Fetching of corresponding data blocks to cache lines is initiated. A processor may enter transactional execution mode and memory instructions of a program may be executed using the prefetched data blocks.

Abstract: Execution of a set of instructions within a transaction is prevented. A processor identifies a first set of instructions in an instruction stream of a transaction. The first set of instructions incurs a first memory access that is not visible to the transaction and will cause the transaction to abort. The processor generates a second set of instructions that incurs a second memory access that is visible to the transaction. The second set of instructions is generated based on the first memory access and first set of instructions. The processor executes, within the transaction, the second set of instructions instead of the first set of instructions.

Abstract: Execution of a set of instructions within a transaction is prevented. A processor identifies a first set of instructions in an instruction stream of a transaction. The first set of instructions incurs a first memory access that is not visible to the transaction and will cause the transaction to abort. The processor generates a second set of instructions that incurs a second memory access that is visible to the transaction. The second set of instructions is generated based on the first memory access and first set of instructions. The processor executes, within the transaction, the second set of instructions instead of the first set of instructions.

Abstract: A transactional memory system salvages a hardware transaction. A processor of the transactional memory system executes a first salvage checkpoint instruction in a code region during transactional execution of the code region, and based on the executing the first salvage checkpoint instruction, the processor records transaction state information comprising an address of the first salvage checkpoint instruction within the code region. The processor detects a pending point of failure in the code region during the transactional execution, and based on the detecting, determines that the transaction state information been recorded, and further based on the detecting, executes an about-to-fail handler. Based on executing the about-to-fail handler, the processor returns to the execution of the code region of the transaction at the address of the checkpoint instruction.

Abstract: In a transactional memory environment including a first processor and one or more additional processors, a computer-implemented method includes, by the first processor, initializing a time record, listening for zero or more probes from the one more additional processors, responding to each probe of the zero or more probes, and logging each probe of the zero or more probes to yield a probe log. The computer-implemented method further includes, by the first processor, receiving a probe report directive and, responsive to the probe report directive, generating a probe report indication based on the probe log. The probe report indication denotes whether, since the time record, the first processor has received any of the zero or more probes. The computer-implemented method further includes ending the time record. A corresponding computer program product and computer system are also disclosed.

Abstract: In a transactional memory environment including a first processor and one or more additional processors, a computer-implemented method includes, by the first processor, initializing a time record, listening for zero or more probes from the one more additional processors, responding to each probe of the zero or more probes, and logging each probe of the zero or more probes to yield a probe log. The computer-implemented method further includes, by the first processor, receiving a probe report directive and, responsive to the probe report directive, generating a probe report indication based on the probe log. The probe report indication denotes whether, since the time record, the first processor has received any of the zero or more probes. The computer-implemented method further includes ending the time record. A corresponding computer program product and computer system are also disclosed.

Abstract: In a transactional memory environment, a computer-implemented method includes receiving one or more memory locations and broadcasting, by a first processor to one or more additional processors, a cross-interrogate. The cross-interrogate includes the one or more memory locations. The computer-implemented method further includes, by the one or more additional processors, receiving the cross-interrogate, not aborting any current transaction based on the cross-interrogate, and generating an indication. The indication comprises whether the one or more memory locations is in use for the current transaction by that of the one or more additional processors. The computer-implemented method further includes sending the indication from each of the one or more additional processors to the first processor and, by the first processor, combining each indication from the one or more additional processors to yield a status code and returning the status code.

Abstract: In a transactional memory environment including a first processor and one or more additional processors, a computer-implemented method includes identifying a memory location and sending a probe request from the first processor to the additional processors. The probe request includes the memory location. The computer implemented method further includes generating, by each additional processor, an indication including whether the memory location is in use for a transaction by the additional processor. The computer-implemented method further includes sending the indication from each additional processor to the first processor and proceeding, by the first processor, based on the indication.

Abstract: In a transactional memory environment, a computer-implemented method includes receiving one or more memory locations and broadcasting, by a first processor to one or more additional processors, a cross-interrogate. The cross-interrogate includes the one or more memory locations. The computer-implemented method further includes, by the one or more additional processors, receiving the cross-interrogate, not aborting any current transaction based on the cross-interrogate, and generating an indication. The indication comprises whether the one or more memory locations is in use for the current transaction by that of the one or more additional processors. The computer-implemented method further includes sending the indication from each of the one or more additional processors to the first processor and, by the first processor, combining each indication from the one or more additional processors to yield a status code and returning the status code.

Abstract: A transactional memory system salvages a hardware transaction. A processor of the transactional memory system executes a first salvage checkpoint instruction in a code region during transactional execution of the code region, and based on the executing the first salvage checkpoint instruction, the processor records transaction state information comprising an address of the first salvage checkpoint instruction within the code region. The processor detects a pending point of failure in the code region during the transactional execution, and based on the detecting, determines that the transaction state information been recorded, and further based on the detecting, executes an about-to-fail handler. Based on executing the about-to-fail handler, the processor returns to the execution of the code region of the transaction at the address of the checkpoint instruction.

Abstract: Discontiguous storage locations are prefetched by a prefetch instruction. Addresses of the discontiguous storage locations are provided by a list directly or indirectly specified by a parameter of the prefetch instruction, along with metadata and information about the list entries. Fetching of corresponding data blocks to cache lines is initiated. A processor may enter transactional execution mode and memory instructions of a program may be executed using the prefetched data blocks.

Abstract: Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued.

Abstract: A transactional memory system predicts the outcome of coalescing outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction, the method comprising. A processor of the transactional memory system determines whether a first plurality of outermost transactions from an associated program that were coalesced experienced an abort, the first plurality of outermost transactions including a first instance of a first transaction. The processor updates a history of the associated program to reflect the results of the determination. The processor coalesces a second plurality of outermost transactions from the associated program, based, at least in part, on the updated history.

Abstract: In a transactional memory environment including a first processor and one or more additional processors, a computer-implemented method includes identifying a memory location and sending a probe request from the first processor to the additional processors. The probe request includes the memory location. The computer implemented method further includes generating, by each additional processor, an indication including whether the memory location is in use for a transaction by the additional processor. The computer-implemented method further includes sending the indication from each additional processor to the first processor and proceeding, by the first processor, based on the indication.

Abstract: In a transactional memory environment including a first processor and one or more additional processors, a computer-implemented method includes identifying a memory location and sending a probe request from the first processor to the additional processors. The probe request includes the memory location. The computer implemented method further includes generating, by each additional processor, an indication including whether the memory location is in use for a transaction by the additional processor. The computer-implemented method further includes sending the indication from each additional processor to the first processor and proceeding, by the first processor, based on the indication.

Abstract: A transactional memory system salvages hardware lock elision (HLE) transactions. A computer system of the transactional memory system records information about locks elided to begin HLE transactional execution of first and second transactional code regions. The computer system detects a pending cache line conflict of a cache line, and based on the detecting stops execution of the first code region of the first transaction and the second code region of the second transaction. The computer system determines that the first lock and the second lock are different locks and uses the recorded information about locks elided to acquire the first lock of the first transaction and the second lock of the second transaction. The computer system commits speculative state of the first transaction and the second transaction and the computer system continues execution of the first code region and the second code region non-transactionally.

Abstract: Techniques relate to handling outstanding cache miss prefetches. A processor pipeline recognizes that a prefetch canceling instruction is being executed. In response to recognizing that the prefetch canceling instruction is being executed, all outstanding prefetches are evaluated according to a criterion as set forth by the prefetch canceling instruction in order to select qualified prefetches. In response to evaluating, a cache subsystem is communicated with to cause canceling of the qualified prefetches that fit the criterion. In response to successful canceling of the qualified prefetches, a local cache is prevented from being updated from the qualified prefetches.

Abstract: Embodiments relate to address probing for a transaction. An aspect includes determining, before starting execution of a transaction, a plurality of addresses that will be used by the transaction during execution. Another aspect includes probing each address of the plurality of addresses to determine whether any of the plurality of addresses has an address conflict. Yet another aspect includes, based on determining that none of the plurality of addresses has an address conflict, starting execution of the transaction.