Abstract: A method, a system and a computer program product for handling speculative stores. The system determines when a speculative store buffer is not full. An indicator is generated when the speculative store buffer is not full, and the speculative stores are input into the speculative store buffer. When the speculative store buffer is full, a full buffer indicator is generated. Speculative stores prevented from entering the speculative store buffer are overflow stores. The overflow list is searched to determine whether one or more addresses of the overflow stores are present in the overflow list. When one or more addresses of the overflow stores are not present in the overflow list, the overflow stores are stored in the overflow list.

Abstract: A method, system and computer program product for issuing one or more software initiated operations for creating a checkpoint of a register file and memory, and for restoring a register file and memory to the checkpointed state. At the execution of a checkpoint operation, the system returns a condition code indicating success or failure. When the condition code is set equal to one, one or more checkpoints are initiated. Contents of the register file and gated store buffer are stored each time the one or more checkpoints are initiated. When the checkpoint is created, the system notifies software when a hardware checkpoint capacity has been reached. One or more of the software checkpoint, hardware checkpoint, and handler checkpoint are utilized to provide a more precise point of restoration. During software execution, the register file and gated store buffer can be restored as defined by the one or more previous checkpoints.

Abstract: A system and method of maintaining consistent cached copies of memory in a multiprocessor system having a main memory, includes a memory directory having entries mapping the main memory and a directory cache having records corresponding to a subset of the memory directory entries. The memory directory is preferably a full map directory having entries mapping all of the main memory or a sparse directory having entries mapping to a subset of the main memory. The method includes the steps of receiving, at the coherence controller, a signal indicative of a processor cache miss or a coherence request associated with a memory line in one of the plurality of compute nodes; determining a target coherence controller from the signal; performing a directory lookup in a directory cache of a compute node associated with the targeted coherence controller to determine a state of the memory line in each cache of the system.