Patents by Inventor MagiC Technologies, Inc.

MagiC Technologies, Inc. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Shared Bit Line SMT MRAM Array with Shunting Transistors Between Bit Lines
    Publication number: 20130301347
    Abstract: An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.
    Type: Application
    Filed: May 4, 2013
    Publication date: November 14, 2013
    Inventors: MagIC Technologies, Inc., International Business Machines Corporation
  • High Performance MTJ Element for Conventional MRAM and for STT-RAM and a Method for Making the Same
    Publication number: 20130154038
    Abstract: A STT-RAM MTJ that minimizes spin-transfer magnetization switching current (Jc) is disclosed. The MTJ has a MgO tunnel barrier layer formed with a natural oxidation process to achieve a low RA (10 ohm-um2) and a Fe or Fe/CoFeB/Fe free layer which provides a lower intrinsic damping constant than a CoFeB free layer. A Fe, FeB, or Fe/CoFeB/Fe free layer when formed with a MgO tunnel barrier (radical oxidation process) and a CoFeB AP1 pinned layer in a MRAM MTJ stack annealed at 360° C. provides a high dR/R (TMR)>100% and a substantial improvement in read margin with a TMR/Rp_cov=20. High speed measurement of 100 nm×200 nm oval STT-RAM MTJs has shown a Jc0 for switching a Fe free layer is one half that for switching an amorphous Co40Fe40B20 free layer. A Fe/CoFeB/Fe free layer configuration allows the Hc value to be increased for STT-RAM applications.
    Type: Application
    Filed: February 11, 2013
    Publication date: June 20, 2013
    Applicant: MAGIC TECHNOLOGIES, INC.
    Inventor: MagiC Technologies, Inc.