Abstract: A capacitive-to-digital converter is provided which includes: sensor, offset and reference capacitors, an integrator circuit and a demodulation circuit. The sensor capacitor is switched according to a first clock and the offset capacitor according to a second clock, which has a higher switching frequency. The reference capacitor is switched according to a return signal from the converter's output. The integrator circuit includes an integrator capacitor, and has first and second nodes, with the sensor, offset and reference capacitors each being switched to the first and second nodes based on the respective first clock, second clock or return signal. The demodulation circuit receives and converts output of the integrator circuit into a digital output. The higher frequency clocking of the offset capacitor allows for a reduction in capacitance of the offset, reference or integrator capacitor, and the multiclocking of the converter allows for use of a multireferencing to the sensor capacitor.

Abstract: A capacitive-to-digital converter is provided which includes: sensor, offset and reference capacitors, an integrator circuit and a demodulation circuit. The sensor capacitor is switched according to a first clock and the offset capacitor according to a second clock, which has a higher switching frequency. The reference capacitor is switched according to a return signal from the converter's output. The integrator circuit includes an integrator capacitor, and has first and second nodes, with the sensor, offset and reference capacitors each being switched to the first and second nodes based on the respective first clock, second clock or return signal. The demodulation circuit receives and converts output of the integrator circuit into a digital output. The higher frequency clocking of the offset capacitor allows for a reduction in capacitance of the offset, reference or integrator capacitor, and the multiclocking of the converter allows for use of a multireferencing to the sensor capacitor.

Abstract: Circuitry is disclosed for the calibration of heating element and ambient temperature sensors, comprising: a) an amplifier having positive and negative inputs, and an output; b) one or more heating MOS transistors selectably coupled in parallel and having 1) a heating transistor drain coupled to the positive input of the amplifier; 2) a heating transistor source configured to receive a supply voltage; and 3) a heating transistor gate coupled to the amplifier output; c) one or more ambient MOS transistors selectably coupled in parallel and having 1) an ambient transistor drain, 2) an ambient transistor gate coupled to the amplifier output; and 3) an ambient transistor source configured to receive the supply voltage; d) a temperature difference resistance configured: 1) to be coupled at least partially between an ambient connection and the ambient transistor drain; and 2) to be coupled at least partially between the ambient connection and the negative input of the amplifier.

Abstract: Circuitry is disclosed for the calibration of heating element and ambient temperature sensors, comprising: a) an amplifier having positive and negative inputs, and an output; b) one or more heating MOS transistors selectably coupled in parallel and having 1) a heating transistor drain coupled to the positive input of the amplifier; 2) a heating transistor source configured to receive a supply voltage; and 3) a heating transistor gate coupled to the amplifier output; c) one or more ambient MOS transistors selectably coupled in parallel and having 1) an ambient transistor drain, 2) an ambient transistor gate coupled to the amplifier output; and 3) an ambient transistor source configured to receive the supply voltage; d) a temperature difference resistance configured: 1) to be coupled at least partially between an ambient connection and the ambient transistor drain; and 2) to be coupled at least partially between the ambient connection and the negative input of the amplifier.