Abstract: In an integrated circuit, a data traffic router includes a number of multiplexors coupled to each other, and to subsystems of the IC. The subsystems selectively output to each other. The data traffic router selectively provides paths for the outputs to reach their destinations, to facilitate concurrent communications between at least two selected combinations of the subsystems.

Abstract: A data transfer interface includes facilities for a subsystem including the data transfer interface to internally prioritize transactions with other subsystems, using facilities of the data transfer interface. In one embodiment, the subsystem also includes with the transactions bus arbitration priorities to facilitate prioritization and granting of access to an on-chip bus to the contending transactions. In one embodiment, an integrated circuit includes the on-chip bus and a number of the subsystems interacting with each other through transactions across the on-chip bus.

Abstract: A data transfer interface includes facilities for a subsystem including the data transfer interface to internally prioritize transactions with other subsystems, using facilities of the data transfer interface. In one embodiment, the subsystem also includes with the transactions bus arbitration priorities to facilitate prioritization and granting of access to an on-chip bus to the contending transactions. In one embodiment, an integrated circuit includes the on-chip bus and a number of the subsystems interacting with each other through transactions across the on-chip bus.

Abstract: In an integrated circuit, a data traffic router includes a number of multiplexors and a controller, coupled to each other, and to subsystems of the IC. The subsystems selectively output to each other. The data traffic router selectively configures itself to provide paths for the outputs to reach their destinations, to facilitate concurrent communications between selected combinations of the subsystems.

Abstract: A digital audio decoder is described. The digital audio decoder includes: (i) an audio core which defines hardware for matrixing and windowing during decoding of MPEG digital audio signals such that matrixing coefficients are multiplied by discrete modified sample values during the matrixing operation; and (ii) an input RAM coupled to the audio core and configured to store the discrete modified sample values calculated outside the audio core in preparation for the matrixing operation and configured to store intermediate values calculated by the audio core during the matrixing operation that are written back to the input RAM. The modified sample values represent either a summation of two samples of MPEG audio data or a difference of the two samples of MPEG audio data. A process of decoding MPEG digital audio signals in a digital audio decoder including a firmware and a hardware, both of which are configured to decode MPEG audio signals, is also described.

Abstract: In an integrated circuit, a data traffic router includes a number of multiplexors and a controller, coupled to each other, and to subsystems of the IC. The subsystems selectively output to each other. The data traffic router selectively configures itself to provide paths for the outputs to reach their destinations, to facilitate concurrent communications between selected combinations of the subsystems.

Abstract: A data transfer interface includes facilities for a subsystem including the data transfer interface to internally prioritize transactions with other subsystems, using facilities of the data transfer interface. In one embodiment, the subsystem also includes with the transactions bus arbitration priorities to facilitate prioritization and granting of access to an on-chip bus to the contending transactions. In one embodiment, an integrated circuit includes the on-chip bus and a number of the subsystems interacting with each other through transactions across the on-chip bus.

Abstract: A memory has a wide data bus to an associative array processor. An entire row of the memory is read to or written by the associative array processor in a single access cycle. A data I/O controller is also coupled to the wide data bus between the memory and associative array processor. The data I/O controller has multiplexers that select one word from the wide data bus for access by a word-width system bus. A block-access mode selects a multi-word block in a row for access. A register latches in a block or row from the wide data bus, and words from the register are then accessed by the data I/O controller. The wide data bus is at least 1024 bits wide, and can be 5760 bits wide, enough for the associative array processor to read an entire line of a graphics or video picture.

Abstract: A digital audio decoder is described. The digital audio decoder includes: (i) an audio core which defines a hardware for sub-band synthesis and windowing during decoding of MPEG and AC-3 digital audio signals; (ii) an input RAM coupled to the audio core and configured to store discrete samples in preparation for the sub-band synthesis and the windowing and configured to store intermediate values that are calculated by the audio core during the sub-band synthesis and written back to the input RAM. A process of decoding MPEG and AC-3 digital audio signals is also described.

Abstract: An audio decoder is provided with a programmable and re-configurable downmixing process. In one embodiment, the audio decoder includes a control module and a data path. The data path is configured to read, scale, add, and write audio samples to and from various audio channel frame buffers. The control module implements state diagrams which specify various control signals for directing the operations of the data path. The control module implements state diagrams for directing windowing and downmixing operations. The order in which these operations are performed may be reconfigurable, i.e. downmixing may be performed before or after windowing. This reconfigurability advantageously permits the system designer to trade a slight audio quality enhancement for a decreased memory requirement for some speaker configurations. The downmixing operation requires scaling coefficients which are provided by the control module.

Abstract: An audio decoder is provided with a programmable and re-configurable downmixing process. In one embodiment, the audio decoder includes a control module and a data path. The data path is configured to read, scale, add, and write audio samples to and from various audio channel frame buffers. The control module implements state diagrams which specify various control signals for directing the operations of the data path. The control module implements state diagrams for directing windowing and downmixing operations. The order in which these operations are performed may be reconfigurable, i.e. downmixing may be performed before or after windowing. This reconfigurability advantageously permits the system designer to trade a slight audio quality enhancement for a decreased memory requirement for some speaker configurations. The downmixing operation requires scaling coefficients which are provided by the control module.

Abstract: A ROM for storing constants used in both the MPEG-2 and AC-3 audio decoding algorithms. These constants include (i) matrixing constants for AC-3 and MPEG audio decoding algorithms and (ii) windowing coefficients for AC-3 and MPEG audio decoding algorithms. The ROM includes (a) a first partition for storing a first set of constants which are windowing coefficients for AC-3 decoding, (b) a second partition for storing a second set of constants which are constants used for pre-IFFT and post-IFFT steps of AC-3 decoding (Blkswflag=1), (c) a third partition for storing a third set of constants which are both IDCT coefficients for MPEG decoding and IFFT coefficients for AC-3 decoding, (d) a fourth partition for storing a fourth set of constants which are constants used for pre-IFFT and post-IFFT steps of AC-3 decoding (Blkswflag=0), and (e) a fifth partition for storing a fifth set of constants which are windowing coefficients for MPEG decoding.

Abstract: A reusable hardware layout ("core") for performing some, but not all, MPEG and AC-3 audio decoding functions. Specifically, the audio core performs matrixing and windowing operations of MPEG and AC-3 decoding. The disclosed audio core design includes a data path, a control logic unit, an input RAM interface (for controlling an input RAM), an output RAM interface (for controlling an output RAM), a ROM, a ROM addressing logic unit, and a registers interface. The input RAM and the output RAM are located outside of the audio core. The control logic unit specifies in which state of multiple states the audio core currently resides, with each of the multiple states specifying one function or group of functions of either the MPEG or AC-3 decoding process. The control logic unit includes an MPEG state machine for generating MPEG state and cycle count information and an AC-3 state machine for generating AC-3 state and cycle count information.