Abstract: Methods, apparatus, and systems relating to a semiconductor device having an ESD function for providing a first ESD current flow in a first path and a second ESD current flow in a second path. The semiconductor device includes a pad for at least one of receiving or transmitting an electrical signal; a victim circuit; an electrostatic discharge (ESD) protection device configured for receiving at least a portion of an ESD current resulting from an ESD event and for protecting the victim circuit from damage from the ESD current; an ESD current control module capable of receiving an ESD current resulting from the ESD event from the pad, wherein the ESD current control module is capable of directing a first ESD current portion through the ESD protection device and a second ESD current portion through the victim circuit.

Abstract: Methods to forming trigger-voltage tunable cascode transistors for an ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including adjacent first-type well areas, over the substrate, each pair of first-type well areas separated by a second-type well area; providing one or more junction areas in each first and second type well area, each junction area being a first type or a second type; forming fins, spaced from each other, perpendicular to and over the first and second type junction areas; and forming junction-type devices by forming electrical connections between the first and second type junction areas in the first-type well areas and the substrate, wherein a first-stage junction-type device in a first-type well area includes stacked first and second type junction areas, and wherein the first-stage junction-type device is adjacent a second-type well area including first and second type junction areas.

Abstract: An electro-static discharge (ESD) protection transistor device includes a plurality of transistor gates that extend parallel to one another in a first direction and a plurality of source/drain diffusion areas that extend parallel to one another in a second direction perpendicular to the first direction. Each source/drain diffusion area comprises a plurality of source/drain areas disposed between respective ones of the plurality of transistor gates. The ESD protection transistor device further includes a source contact positioned over each source area of the plurality of source areas and a drain contact positioned over each drain area of the plurality of drain areas. With respect to each source/drain diffusion area of the plurality of source/drain diffusion areas, the source contacts are offset from the drain contacts with respect to the first direction.

Abstract: Methods, apparatus, and systems relating to a MOSFET with ESD resistance, specifically, to a semiconductor device comprising a field-effect transistor (FET) comprising a gate, a source, and a drain, all extending parallel to each other in a first direction; at least one source electrostatic discharge (ESD) protection circuit; a source terminal disposed above and in electrical contact with the at least one source ESD protection circuit, wherein the source terminal extends in the first direction; at least one drain ESD protection circuit; and a drain terminal disposed above and in electrical contact with the at least one drain ESD protection circuit, wherein the drain terminal extends in the first direction.

Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a heavily doped source area having conductivity determining impurities at a heavily doped source concentration and a lightly doped drain area having conductivity determining impurities at a lightly doped drain concentration less than the heavily doped source concentration. A drain conductor directly contacts the lightly doped drain area, and a channel is positioned between the heavily doped source area and the lightly doped drain area. A gate overlies the channel.

Abstract: An electrostatic discharge (ESD) device for an integrated circuit includes a substrate having a longitudinally extending fin dispose thereon. A first n-type FinFET (NFET) is disposed within the fin. The NFET includes an n-type source, an n-type drain and a p-well disposed within the substrate under the source and drain. A p-type FinFET (PFET) is disposed within the fin. The PFET includes a p-type source/drain region and an n-well disposed within the substrate under the source/drain region. The n-well and p-well are located proximate enough to each other to form an np junction therebetween. The p-type source/drain region of the PFET and the n-type drain of the NFET are electrically connected to a common input node.

Abstract: Methods to forming trigger-voltage tunable cascode transistors for an ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including adjacent first-type well areas, over the substrate, each pair of first-type well areas separated by a second-type well area; providing one or more junction areas in each first and second type well area, each junction area being a first type or a second type; forming fins, spaced from each other, perpendicular to and over the first and second type junction areas; and forming junction-type devices by forming electrical connections between the first and second type junction areas in the first-type well areas and the substrate, wherein a first-stage junction-type device in a first-type well area includes stacked first and second type junction areas, and wherein the first-stage junction-type device is adjacent a second-type well area including first and second type junction areas.

Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.

Abstract: There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.

Abstract: An electro-static discharge (ESD) protection transistor device includes a plurality of transistor gates that extend parallel to one another in a first direction and a plurality of source/drain diffusion areas that extend parallel to one another in a second direction perpendicular to the first direction. Each source/drain diffusion area comprises a plurality of source/drain areas disposed between respective ones of the plurality of transistor gates. The ESD protection transistor device further includes a source contact positioned over each source area of the plurality of source areas and a drain contact positioned over each drain area of the plurality of drain areas. With respect to each source/drain diffusion area of the plurality of source/drain diffusion areas, the source contacts are offset from the drain contacts with respect to the first direction.

Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.

Abstract: High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.

Abstract: There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.

Abstract: A circuit for electrostatic discharge (ESD) protection is disclosed. The circuit includes multiple transistors that are selectively turned on during an ESD event. An ESD sense circuit detects an ESD event and asserts signals to activate an ESD protection circuit which closes multiple protection transistors to dissipate current during the ESD event. During normal operation of the circuit, the signals are de-asserted, disabling the ESD protection circuit.

Abstract: There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.

Abstract: An ESD device is provided for protecting a circuit from electrostatic discharge, and includes a planar diode having an anode and a cathode. The anode is electrically coupled to a signal path of the circuit, and the cathode is electrically coupled to a ground of the circuit. The ESD device is configured to be off during normal operation of the circuit and to turn on in response to an electrostatic discharge on the signal path. Two depletion regions in the device are separated by an isolation well. In response to the electrostatic discharge, the depletion regions modulate (e.g., widen and merge), providing a path for the discharge to the ground of the circuit.

Abstract: There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.

Abstract: Protecting non-planar output transistors from electrostatic discharge (ESD) events includes providing a non-planar semiconductor structure, the structure including a semiconductor substrate with a well of n-type or p-type. The provided non-planar structure further includes raised semiconductor structure(s) coupled to the substrate, non-planar transistor(s) of a type opposite the well, each transistor being situated on one of the raised structure(s), the non-planar transistor(s) each including a source, a drain and a gate, the non-planar structure further including parasitic bipolar junction transistor(s) (BJT(s)) on the raised structure(s), each BJT including a collector and an emitter situated on the raised structure and a base being the well, and a well contact for the base of the BJT.

Abstract: An ESD device is provided for protecting a circuit from electrostatic discharge, and includes a planar diode having an anode and a cathode. The anode is electrically coupled to a signal path of the circuit, and the cathode is electrically coupled to a ground of the circuit. The ESD device is configured to be off during normal operation of the circuit and to turn on in response to an electrostatic discharge on the signal path. Two depletion regions in the device are separated by an isolation well. In response to the electrostatic discharge, the depletion regions modulate (e.g., widen and merge), providing a path for the discharge to the ground of the circuit.

Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.