Patents by Inventor Mahadevamurty Nemani
Mahadevamurty Nemani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11783042Abstract: Resource access control in a system-on-chip (“SoC”) may employ an agent executing on a processor of the SoC and a trust management engine of the SoC. The agent, such as, for example, a high-level operating system or a hypervisor, may be configured to allocate a resource comprising a memory region to an access domain and to load a software image associated with the access domain into the memory region. The trust management engine may be configured to lock the resource against access by any entity other than the access domain, to authenticate the software image associated with the access domain, and to initiate booting of the access domain in response to a successful authentication of the software image associated with the access domain.Type: GrantFiled: June 17, 2020Date of Patent: October 10, 2023Assignee: QUALCOMM IncorporatedInventors: Steven Halter, Samar Asbe, Miguel Ballesteros, Girish Bhat, Mahadevamurty Nemani
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Publication number: 20210397714Abstract: Resource access control in a system-on-chip (“SoC”) may employ an agent executing on a processor of the SoC and a trust management engine of the SoC. The agent, such as, for example, a high-level operating system or a hypervisor, may be configured to allocate a resource comprising a memory region to an access domain and to load a software image associated with the access domain into the memory region. The trust management engine may be configured to lock the resource against access by any entity other than the access domain, to authenticate the software image associated with the access domain, and to initiate booting of the access domain in response to a successful authentication of the software image associated with the access domain.Type: ApplicationFiled: June 17, 2020Publication date: December 23, 2021Inventors: Steven HALTER, Samar ASBE, Miguel BALLESTEROS, Girish BHAT, Mahadevamurty NEMANI
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Publication number: 20210365557Abstract: A method for external access control to protect system-on-chip (SoC) subsystems and stored subsystem assets is described. The method includes sensing, during a cold boot of an SoC hardware system, a debug fuse vector for access to SoC subsystems of an SoC owner and/or third-party subsystems of an SoC hardware architecture. The method also includes disabling access to each SoC subsystem with a blown fuse in the debug fuse vector. The method further includes re-enabling, by a secure root of trust, access to an SoC subsystem and/or a third-party subsystem for an external debugger when authentication of one or more debug certificates of a third-party owner of the external debugger is successful.Type: ApplicationFiled: May 21, 2020Publication date: November 25, 2021Inventors: Jaydeep CHOKSHI, Miguel BALLESTEROS, Mahadevamurty NEMANI, Samar ASBE, Girish BHAT, Alan YOUNG, Victor WONG, Steven HALTER
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Publication number: 20210124818Abstract: In illustrative examples described herein, a hardware-based mechanism is provided to prevent brute force attacks on user credentials. In some examples, a throttling policy is added to a hardware key manager to provide timer-based throttling using a secure hardware timer. A register or slot in hardware is used to maintain throttling policy attributes or parameters for tracking a throttle count and a timeout value to be enforced. During a cryptographic wrap operation, a user key is associated with, or bound to, the slot or register. During a subsequent unwrap operation, the hardware key manager then enforces any needed timeouts by throttling user access in response to any incorrect entries based on the throttling policy attributes or parameters maintained in the slot or register. Examples exploiting an always-on battery-backed processing island are also provided. In some examples, throttling is implemented without the use of any secure storage.Type: ApplicationFiled: October 23, 2019Publication date: April 29, 2021Inventors: Baranidharan MUTHUKUMARAN, Satish ANAND, Mahadevamurty NEMANI, Ivan MCLEAN, Miguel BALLESTEROS
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Patent number: 9519041Abstract: Systems and methods for calibrating on-die analog current sensors are disclosed. The methods can be routinely applied to perform a calibration such as during a system initialization or boot procedure or during other times when the system is in a sleep or power saving mode of operation. The systems determine a leakage current in the device under present environmental conditions. A baseline load current determined under the present temperature and input voltage is retrieved and used to determine a total leakage current. A reproducible and stable dynamic load is controllably applied to provide a known current to the on-die analog current sensor. A third mechanism permits repeatable adjustments to the known current that span the operational range of the on-die integrated current sensor. The responsiveness of the disclosed mechanisms ensures that temperature induced leakage does not increase significantly during a current sensor calibration.Type: GrantFiled: August 21, 2014Date of Patent: December 13, 2016Assignee: QUALCOMM INCORPORATEDInventor: Mahadevamurty Nemani
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Publication number: 20160070327Abstract: Various embodiments of methods and systems for managing current consumption in a portable computing device (“PCD”) are disclosed. A duration of time associated with a maximum allowable current consumption through a voltage regulator is divided into a plurality of N sub-durations. The current consumption for each sub-duration is monitored and a moving sum of current consumption is calculated for a plurality of past sub-durations. Using the sum of current consumption, a current budget for a next sub-duration or next set of consecutive sub-durations may be determined. Subsequently, throttling levels of power consuming processing components may be adjusted such that a maximum allowable current consumption over consecutive N sub-durations may be maintained beneath a peak current threshold without unnecessarily sacrificing processing capacity of the processing components.Type: ApplicationFiled: September 8, 2014Publication date: March 10, 2016Inventors: MAHADEVAMURTY NEMANI, JEFFREY RUNNER, NILANJAN BANERJEE
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Publication number: 20160054422Abstract: Systems and methods for calibrating on-die analog current sensors are disclosed. The methods can be routinely applied to perform a calibration such as during a system initialization or boot procedure or during other times when the system is in a sleep or power saving mode of operation. The systems determine a leakage current in the device under present environmental conditions. A baseline load current determined under the present temperature and input voltage is retrieved and used to determine a total leakage current. A reproducible and stable dynamic load is controllably applied to provide a known current to the on-die analog current sensor. A third mechanism permits repeatable adjustments to the known current that span the operational range of the on-die integrated current sensor. The responsiveness of the disclosed mechanisms ensures that temperature induced leakage does not increase significantly during a current sensor calibration.Type: ApplicationFiled: August 21, 2014Publication date: February 25, 2016Inventor: MAHADEVAMURTY NEMANI
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Patent number: 7345947Abstract: Embodiments of the invention provide techniques for reducing standby power consumption due to leakage currents in memory circuits. In some embodiments, systems are provided with one or more processors having) bit cells coupled to a word-line node and to a virtual ground node. The word-line node is to be at an active word-line voltage when the row is active and an inactive word-line voltage when the row is inactive. The virtual ground node is to be at an operational ground voltage when the memory array is enabled and at an elevated voltage when the memory array is in a standby mode. There is also a word-line driver circuit coupled to the bit cells through the word-line and virtual ground nodes. The current leakage in the bit cells and word-line driver circuit is reduced during the standby mode when the virtual ground node is at the elevated voltage.Type: GrantFiled: September 5, 2006Date of Patent: March 18, 2008Assignee: Intel CorporationInventors: Jeffrey L. Miller, Mahadevamurty Nemani, James W. Conary
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Patent number: 7164616Abstract: Disclosed herein are techniques for reducing standby power consumption due to leakage currents in memory array circuits.Type: GrantFiled: December 20, 2004Date of Patent: January 16, 2007Assignee: Intel CorporationInventors: Jeffrey L. Miller, Mahadevamurty Nemani, James W. Conary
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Publication number: 20070002673Abstract: Disclosed herein are techniques for reducing standby power consumption due to leakage currents in memory circuits.Type: ApplicationFiled: September 5, 2006Publication date: January 4, 2007Inventors: Jeffrey Miller, Mahadevamurty Nemani, James Conary
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Publication number: 20060133185Abstract: Disclosed herein are techniques for reducing standby power consumption due to leakage currents in memory array circuits.Type: ApplicationFiled: December 20, 2004Publication date: June 22, 2006Inventors: Jeffrey Miller, Mahadevamurty Nemani, James Conary
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Patent number: 6922798Abstract: Apparatus and methods for providing enhanced redundancy for a cache are provided. For example, an on-die cache is disclosed which includes a first memory array having a defective array line; a second memory array having a defective array line; and a redundant memory array having a plurality of array lines. A first one of the array lines is mapped to the defective array line of the first array and a second one of the array lines is mapped to the defective array line of the second array.Type: GrantFiled: July 31, 2002Date of Patent: July 26, 2005Assignee: Intel CorporationInventors: Mahadevamurty Nemani, Kenneth R. Smits
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Publication number: 20040025095Abstract: Apparatus and methods for providing enhanced redundancy for a cache are provided. For example, an on-die cache is disclosed which includes a first memory array having a defective array line; a second memory array having a defective array line; and a redundant memory array having a plurality of array lines. A first one of the array lines is mapped to the defective array line of the first array and a second one of the array lines is mapped to the defective array line of the second array.Type: ApplicationFiled: July 31, 2002Publication date: February 5, 2004Inventors: Mahadevamurty Nemani, Kenneth R. Smits
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Patent number: 6631444Abstract: Architecture for a cache fabricated on a die with a processor including a plurality of cache banks, each containing a plurality of storage cell subarrays, the cache banks being arranged in physical relationship to a central location on the die that provides a point for information transfer between the processor and the cache. A data path provides synchronous transmission of data to/from the cache banks such that data requested by the processor in a given clock cycle is received at the central location a predetermined number of clock cycles later regardless of which cache bank in the cache the data is stored.Type: GrantFiled: June 27, 2001Date of Patent: October 7, 2003Assignee: Intel CorporationInventors: Kenneth R. Smits, Bharat Bhushan, Mahadevamurty Nemani
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Publication number: 20030005224Abstract: Architecture for a cache fabricated on a die with a processor including a plurality of cache banks, each containing a plurality of storage cell subarrays, the cache banks being arranged in physical relationship to a central location on the die that provides a point for information transfer between the processor and the cache. A data path provides synchronous transmission of data to/from the cache banks such that data requested by the processor in a given clock cycle is received at the central location a predetermined number of clock cycles later regardless of which cache bank in the cache the data is stored.Type: ApplicationFiled: June 27, 2001Publication date: January 2, 2003Applicant: Intel CorporationInventors: Kenneth R. Smits, Bharat Bhushan, Mahadevamurty Nemani
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Patent number: 6327552Abstract: A method, system and computer program product for automatically determining optimal design parameters of a subsystem to meet design constraints. The subsystem comprises a plurality of circuits. The optimal design parameters are determined by performing a parameter-delay curve optimization of the subsystem design parameters. Specifically, an embodiment of the present invention provides a method and/or computer program product for determining optimal values for the design parameters of a circuit block, which result in optimally assigned delay targets for datapath blocks at the minimum power/area point. The problem/solution space is extended to solve the problem of figuring out the best possible implementation, for example, static vs dynamic, for each datapath block. Based on parameter functions, which relate to the design parameters for circuits in the circuit block, the design parameters are optimized to satisfy the design constraints.Type: GrantFiled: December 28, 1999Date of Patent: December 4, 2001Assignee: Intel CorporationInventors: Mahadevamurty Nemani, Franklin Baez
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Publication number: 20010032067Abstract: A method, system and computer program product for automatically determining optimal design parameters of a subsystem to meet design constraints. The subsystem comprises a plurality of circuits. The optimal design parameters are determined by performing a parameter-delay curve optimization of the subsystem design parameters.Type: ApplicationFiled: December 28, 1999Publication date: October 18, 2001Inventors: MAHADEVAMURTY NEMANI, FRANKLIN BAEZ
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Patent number: 6111435Abstract: A circuit includes first and second pull-up transistors having first and second drains, respectively, each coupled to separate voltage clamps. The gates of each of the two pull-up transistors are coupled to a clock signal line. The circuit further includes a shared pull-down transistor, the gate of which is coupled to the clock signal line. The drain of the shared pull-down transistor is coupled to the first drain via at least one pull-down transistor in series with the shared pull-down transistor. The drain of the shared pull-down transistor is also coupled to the second drain via at least one pull-down transistor in series with the shared pull-down transistor. This circuit may be found useful in multiplexing applications.Type: GrantFiled: June 30, 1999Date of Patent: August 29, 2000Assignee: Intel CorporationInventors: Jiann-Cherng James Lan, Mahadevamurty Nemani, Narsing K. Vijayrao, Wenjie Jiang, Sudarshan Kumar