Patents by Inventor Mahadevan Ganapathi

Mahadevan Ganapathi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus using a memory model
    Patent number: 6053948
    Abstract: A computer system including a memory model of a memory circuit. The computer system comprises a processor coupled to receive and manipulate the memory model, and a memory including the memory model. The memory model includes: a number of address bits corresponding to a number of address bits of the memory circuit; a number of data bits corresponding to a number of data bits of the memory circuit; and a memory type parameter corresponding to a type of the memory circuit.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: April 25, 2000
    Assignee: Synopsys, Inc.
    Inventors: Radha Vaidyanathan, Emil F. Girczyc, Sivaram Krishna Nayudu, Mahadevan Ganapathi
  • Simulator including process levelization
    Patent number: 5784593
    Abstract: A method of preparing a specification of a system for simulation on a computer system. The specification includes a hardware design language specification of the system. Analyze the specification to identify a set of processes, where each process includes a plurality of statements. Determine an evaluation order of the set of processes. Generate a combined process including a portion of the plurality of statements. The portion of the plurality of statements are included in the combined process so as to be evaluated according to the evaluation order.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: July 21, 1998
    Assignee: Synopsys, Inc.
    Inventors: Ping-sheng Tseng, Radha Vaidyanathan, Sivaram Krishna Nayudu, Mahadevan Ganapathi