Abstract: In some embodiments, coaxial plated through holes (PTH) for robust electrical performance are presented. in this regard, an apparatus is introduced comprising an integrated circuit device and a substrate coupled with the integrated circuit device, wherein the substrate includes: a plated through hole, the plated through hole filled with dielectric material and a coaxial copper wire, and conductive traces to separately route the plated through hole and the coaxial copper wire. Other embodiments are also disclosed.

Abstract: In some embodiments, coaxial plated through holes (PTH) for robust electrical performance are presented. In this regard, an apparatus is introduced comprising an integrated circuit device and a substrate coupled with the integrated circuit device, wherein the substrate includes: a plated through hole, the plated through hole filled with dielectric material and a coaxial copper wire, and conductive traces to separately route the plated through hole and the coaxial copper wire. Other embodiments are also disclosed and claimed.

Abstract: A coreless substrate includes a stiffener material (110, 210, 620) having a plated via (120, 320) formed therein, an electrically insulating material (130, 230, 830) above the stiffener material, and an electrically conductive material (140, 240, 840) in the electrically insulating layer. In the same or another embodiment, a package for a microelectronic device includes a stiffener material layer (115, 215, 615) having plated vias (120, 320) formed therein and further having a recess (118, 218) therein, build-up layers (150, 350, 850) over the stiffener material layer, and a die (370) attached over the build-up layers. The stiffener material layer and the build-up layers form a coreless substrate (100, 380, 910, 920) of the package. The coreless substrate has a surface (381), and the die covers less than all of the surface of the coreless substrate such that the surface has at least one exposed region (382).

Abstract: A microelectronic package includes a first substrate (120) having a first surface area (125) and a second substrate (130) having a second surface area (135). The first substrate includes a first set of interconnects (126) having a first pitch (127) at a first surface (121) and a second set of interconnects (128) having a second pitch (129) at a second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes a third set of interconnects (236) having a third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with a microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

Abstract: In some embodiments, coaxial plated through holes (PTH) for robust electrical performance are presented. In this regard, an apparatus is introduced comprising an integrated circuit device and a substrate coupled with the integrated circuit device, wherein the substrate includes: a plated through hole, the plated through hole filled with dielectric material and a coaxial copper wire, and conductive traces to separately route the plated through hole and the coaxial copper wire. Other embodiments are also disclosed and claimed.

Abstract: A coreless substrate includes a stiffener material (110, 210, 620) having a plated via (120, 320) formed therein, an electrically insulating material (130, 230, 830) above the stiffener material, and an electrically conductive material (140, 240, 840) in the electrically insulating layer. In the same or another embodiment, a package for a microelectronic device includes a stiffener material layer (115, 215, 615) having plated vias (120, 320) formed therein and further having a recess (118, 218) therein, build-up layers (150, 350, 850) over the stiffener material layer, and a die (370) attached over the build-up layers. The stiffener material layer and the build-up layers form a coreless substrate (100, 380, 910, 920) of the package. The coreless substrate has a surface (381), and the die covers less than all of the surface of the coreless substrate such that the surface has at least one exposed region (382).

Abstract: An apparatus for routing a high-speed signal is disclosed, having a signal router and a plurality of projections extending therefrom. The projections are separated from each other by a distance between about 0.25 and 0.125 of ?go, wherein ?go is a guide wavelength at cut-off frequency of the first signal transmitting element.

Abstract: In some embodiments, an array capacitor for decoupling multiple voltages is presented. In this regard, an array capacitor is introduced having two electrically isolated capacitor regions. Other embodiments are also disclosed and claimed.

Abstract: An embodiment of the present invention is a technique to fabricate a package. Signals are routed in a signal layer on top of a substrate. Contacts are formed between the routed signals. The contacts are connected to a ground layer. A conductive layer is deposited, by surface mounting, on the substrate to connect to the contacts.

Abstract: In some embodiments, an article of manufacture includes a metal layer and a first dielectric layer in contact with a first face of the metal layer. The article of manufacture also includes a second dielectric layer in contact with a second face of the metal layer. The second face of the metal layer is opposite to the first face of the metal layer. The metal layer may be a continuous sheet having slots formed therein to allow the first and second dielectric layers to adhere to each other by way of the slots.

Abstract: An apparatus for routing a high-speed signal is disclosed, having a signal router and a plurality of projections extending therefrom. The projections are separated from each other by a distance between about 0.25 and 0.125 of ?go, wherein ?go is a guide wavelength at cut-off frequency of the first signal transmitting element.

Abstract: In some embodiments, an article of manufacture includes a metal layer and a first dielectric layer in contact with a first face of the metal layer. The article of manufacture also includes a second dielectric layer in contact with a second face of the metal layer. The second face of the metal layer is opposite to the first face of the metal layer. The metal layer may be a continuous sheet having slots formed therein to allow the first and second dielectric layers to adhere to each other by way of the slots.

Abstract: A package with increased capacitance comprises a core and a plurality of buildup layers. The core has an inner dielectric portion and the core outer conductive layer. The buildup layers are disposed over the core and have offset ablated regions reducing the thickness of the buildup layers in the ablated regions. Conductive material is plated on the buildup layers including within the ablated regions. The reduced thickness and increased plate area due to the ablated regions increases the capacitance between adjacent buildup layers. Processors and processing systems may take advantage of the increased capacitance in the package to draw more current and operate at higher data rates.