Patents by Inventor Mahak Gupta

Mahak Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230114164
    Abstract: In a further embodiment, a system on a chip integrated circuit (SoC) is provided that includes an active base die including a first cache memory, a first die mounted on and coupled with the active base die, and a second die mounted on the active base die and coupled with the active base die and the first die. The first die includes an interconnect fabric, an input/output interface, and an atomic operation handler. The second die includes an array of graphics processing elements and an interface to the first cache memory of the active base die. At least one of the graphics processing elements are configured to perform, via the atomic operation handler, an atomic operation to a memory device.
    Type: Application
    Filed: December 15, 2021
    Publication date: April 13, 2023
    Applicant: Intel Corporation
    Inventors: Rahul Pal, Aravindh Anantaraman, Lakshminarayana Pappu, Dongsheng Bi, Guadalupe J. Garcia, Altug Koker, Joydeep Ray, Rahul Joshi, Shrikul Atulkumar Joshi, Mahak Gupta
  • Patent number: 9170946
    Abstract: Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 27, 2015
    Assignee: Intel Corporation
    Inventors: Herbert H. Hum, James R. Vash, Eric A. Gouldey, Ganesh Kumar, David Bubien, Manoj K. Arora, Luke Chang, Lavanya Nama, Mahak Gupta
  • Publication number: 20140181394
    Abstract: Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Inventors: Herbert H. Hum, James R. Vash, Eric A. Gouldey, Ganesh Kumar, David Bubien, Manoj K. Arora, Luke Chang, Lavanya Nama, Mahak Gupta