Abstract: An electronic device, e.g. an integrated circuit, is formed on a P-type lightly-doped semiconductor substrate having an N-type buried layer. First and second N-wells extend from a surface of the substrate to the buried layer. A first NSD region is located within the first N-well, and a second NSD region is located within the second N-well. A PSD region extends from the substrate surface into the substrate and is located between the first and second NSD regions. A P-type lightly-doped portion of the substrate is located between the N-well and the substrate surface and between the PSD region and the first and second NSD regions.

Abstract: An integrated circuit contains a logic MOS transistor and a memory MOS transistor of a same polarity. The logic MOS transistor has a logic channel stop layer. The memory MOS transistor has a memory channel stop layer. An average dopant density of the memory channel stop layer is higher than an average dopant density of the logic channel stop layer. The integrated circuit is formed by forming a global mask which exposes both the logic and memory MOS transistors. A global channel stop dose of dopants is implanted in the logic and memory MOS transistors. A memory mask is formed which exposes the memory MOS transistor and covers the logic MOS transistor. A memory channel stop dose of dopants of the same polarity is implanted into the memory MOS transistors. The memory channel stop dose of dopants is blocked from the logic MOS transistors.

Abstract: An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode.

Abstract: A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench.

Abstract: An integrated circuit may include a metal gate which extends over an active area and onto an isolation dielectric layer. A conductive spline is formed on the metal gate, extending on the metal gate over at least a portion of the isolation dielectric layer, and extending on the metal gate for a length at least four times a width of the metal gate.

Abstract: A method of fabricating an integrated circuit (IC) includes providing a substrate having a semiconductor surface layer thereon including a field dielectric in a portion of the semiconductor surface layer and a pair of matched devices in at least one of a CMOS area, BiCMOS area, bipolar transistor area, and a resistor area. Dopants are ion implanted into the at least one of the CMOS area, the BiCMOS area, the bipolar transistor area, and the resistor area. The substrate is annealed in a processing chamber of a rapid thermal processor (RTP). The annealing comprises an initial temperature stabilization step including first annealing at a lower temperature for a first time of at least 20 seconds, and then a second annealing comprising ramping from the lower temperature to a peak higher temperature that is at least 100° C. higher (>) than the lower temperature.

Abstract: A method of limiting plasma charging damage on ICs. A die includes gate stacks on active areas defined by a field dielectric. A pre-metal dielectric (PMD) layer is over the gate electrode. A contact masking material pattern is defined on the PMD layer including first contact defining features for forming active contacts and second contact defining features for forming dummy contacts (DC's) including over active areas and gate electrodes. Contacts are etched through the PMD layer using the contact masking material pattern to form active contacts and DC's. A patterned metal 1 (M1) layer is formed including first M1 portions over the active contacts and dummy M1 portions over the DC's. Metallization processing follows including forming interconnects so that the active contacts are connected to MOS transistors on the IC, and the DC's are not electrically connected to the MOS transistors.

Abstract: An integrated circuit containing MOS transistors with replacement gates may be formed with elevated LDD regions and/or recessed replacement gates on a portion of the transistors. Elevating the LDD regions is accomplished by a selective epitaxial process prior to LDD implant. Recessing the replacement gates is accomplished by etching substrate material after removal of sacrificial gate material and before formation of a replacement gate dielectric layer. Elevating the LDD regions and recessing the replacement gates may increase a channel length of the MOS transistors and thereby desirably increase threshold uniformity of the transistors.

Abstract: A method of forming an IC includes providing a field dielectric in a portion of a semiconductor surface, a bipolar or Schottky diode (BSD) class device area, a CMOS transistor area, and a resistor area. A polysilicon layer is deposited to provide a polysilicon gate area for MOS transistors in the CMOS transistor area, over the BSD class device area, and over the field dielectric for providing a polysilicon resistor in the resistor area. A first mask pattern is formed on the polysilicon layer. Using the first mask pattern, first implanting (I1) of the polysilicon resistor providing a first projected range (RP1)<a thickness of the polysilicon layer and second implanting (I2) providing a second RP(RP2), where RP2>RP1. I2 provides a CMOS implant into the semiconductor surface layer in the CMOS transistor area and/or a BSD implant into the semiconductor surface layer in the BSD area.

Abstract: A method of limiting plasma charging damage on ICs. A die includes gate stacks on active areas defined by a field dielectric. A pre-metal dielectric (PMD) layer is over the gate electrode. A contact masking material pattern is defined on the PMD layer including first contact defining features for forming active contacts and second contact defining features for forming dummy contacts (DC's) including over active areas and gate electrodes. Contacts are etched through the PMD layer using the contact masking material pattern to form active contacts and DC's. A patterned metal 1 (M1) layer is formed including first M1 portions over the active contacts and dummy M1 portions over the DC's. Metallization processing follows including forming interconnects so that the active contacts are connected to MOS transistors on the IC, and the DC's are not electrically connected to the MOS transistors.

Abstract: An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.

Abstract: An integrated circuit contains a logic MOS transistor and a memory MOS transistor of a same polarity. The logic MOS transistor has a logic channel stop layer. The memory MOS transistor has a memory channel stop layer. An average dopant density of the memory channel stop layer is higher than an average dopant density of the logic channel stop layer. The integrated circuit is formed by forming a global mask which exposes both the logic and memory MOS transistors. A global channel stop dose of dopants is implanted in the logic and memory MOS transistors. A memory mask is formed which exposes the memory MOS transistor and covers the logic MOS transistor. A memory channel stop dose of dopants of the same polarity is implanted into the memory MOS transistors. The memory channel stop dose of dopants is blocked from the logic MOS transistors.

Abstract: A method of fabricating a CMOS integrated circuit (IC) includes implanting a first n-type dopant at a first masking level that exposes a p-region of a substrate surface having a first gate stack thereon to form NLDD regions for forming n-source/drain extension regions for at least a portion of a plurality of n-channel MOS (NMOS) transistors on the IC. A p-type dopant is implanted at a second masking level that exposes an n-region in the substrate surface having a second gate stack thereon to form PLDD regions for at least a portion of a plurality of p-channel MOS (PMOS) transistors on the IC. A second n-type dopant is retrograde implanted including through the first gate stack to form a deep nwell (DNwell) for the portion of NMOS transistors. A depth of the DNwell is shallower below the first gate stack as compared to under the NLDD regions.

Abstract: An integrated circuit contains a logic MOS transistor and a memory MOS transistor of a same polarity. The logic MOS transistor has a logic channel stop layer. The memory MOS transistor has a memory channel stop layer. An average dopant density of the memory channel stop layer is higher than an average dopant density of the logic channel stop layer. The integrated circuit is formed by forming a global mask which exposes both the logic and memory MOS transistors. A global channel stop dose of dopants is implanted in the logic and memory MOS transistors. A memory mask is formed which exposes the memory MOS transistor and covers the logic MOS transistor. A memory channel stop dose of dopants of the same polarity is implanted into the memory MOS transistors. The memory channel stop dose of dopants are blocked from the logic MOS transistors.

Abstract: A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls, The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.

Abstract: A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench

Abstract: A method of forming an IC includes providing a field dielectric in a portion of a semiconductor surface, a bipolar or Schottky diode (BSD) class device area, a CMOS transistor area, and a resistor area. A polysilicon layer is deposited to provide a polysilicon gate area for MOS transistors in the CMOS transistor area, over the BSD class device area, and over the field dielectric for providing a polysilicon resistor in the resistor area. A first mask pattern is formed on the polysilicon layer. Using the first mask pattern, first implanting (I1) of the polysilicon resistor providing a first projected range (RP1)<a thickness of the polysilicon layer and second implanting (I2) providing a second RP(RP2), where RP2>RP1. I2 provides a CMOS implant into the semiconductor surface layer in the CMOS transistor area and/or a BSD implant into the semiconductor surface layer in the BSD area.

Abstract: An integrated circuit contains a logic MOS transistor and a memory MOS transistor of a same polarity. The logic MOS transistor has a logic channel stop layer. The memory MOS transistor has a memory channel stop layer. An average dopant density of the memory channel stop layer is higher than an average dopant density of the logic channel stop layer. The integrated circuit is formed by forming a global mask which exposes both the logic and memory MOS transistors. A global channel stop dose of dopants is implanted in the logic and memory MOS transistors. A memory mask is formed which exposes the memory MOS transistor and covers the logic MOS transistor. A memory channel stop dose of dopants of the same polarity is implanted into the memory MOS transistors. The memory channel stop dose of dopants are blocked from the logic MOS transistors.

Abstract: A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench.

Abstract: A method of forming an IC includes providing a field dielectric in a portion of a semiconductor surface, a bipolar or Schottky diode (BSD) class device area, a CMOS transistor area, and a resistor area. A polysilicon layer is deposited to provide a polysilicon gate area for MOS transistors in the CMOS transistor area, over the BSD class device area, and over the field dielectric for providing a polysilicon resistor in the resistor area. A first mask pattern is formed on the polysilicon layer. Using the first mask pattern, first implanting (I1) of the polysilicon resistor providing a first projected range (RP1)<a thickness of the polysilicon layer and second implanting (I2) providing a second RP (RP2), where RP2>RP1. I2 provides a CMOS implant into the semiconductor surface layer in the CMOS transistor area and/or a BSD implant into the semiconductor surface layer in the BSD area.