Abstract: An integrated multicelled thyristor includes a plurality of main thyristor cells and a plurality of edge thyristor cells. The main thyristor cells comprise source cells located in the center or innermost portion of an integrated thyristor and the edge cells are located at the periphery. In order to insure that all thyristor cells turn off uniformly, current exporting means is provided from the source cells to the edge cells to reduce current hole crowding in the peripheral cells. The anodes of all cells are electrically connected and the cathodes of all main cells are electrically connected. However, the cathodes of the edge cells are electrically connected to one or more source cells by the current exporting means. The unit cell of the multicelled device preferably comprises a BRT, but can comprise other well known thyristor structures where turn-off is limited by hole-current crowding.

Abstract: An emitter switched thyristor with base resistance control for preventing parasitic latch-up includes a P-N-P-N main thyristor with an N.sup.+ floating emitter for MOS-gated controlled turn-on and a lateral P-channel MOSFET for shunting hole current in a second base region to a P.sup.+ diverting region electrically connected to the cathode. The P-channel MOSFET is enabled by the application of a negative gate voltage to form a P-type inversion layer between the second base region and the P.sup.+ diverter region, thus reducing the resistance between the cathode and the second base region and raising the holding current of the emitter switched thyristor to above the operating current level. The formation of an alternative current path to the cathode has the further effect of reducing the forward bias across the base-emitter junction of an adjacent parasitic thyristor to thereby prevent the sustained regenerative action of the parasitic thyristor.