Patents by Inventor Mahantesh Narwade

Mahantesh Narwade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9886753
    Abstract: A method for controlling the functional output of a verification tool upon receipt of a circuit description comprises searching for a predetermined base pattern in the circuit description. The method further comprises searching for predetermined sub-patterns that are assigned to the base pattern, in the circuit description. The method further comprises the validation of each found sub-pattern based on a predetermined rule to minimize the set of reported errors that based on verification of the circuit description.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: February 6, 2018
    Assignee: Synopsys, Inc.
    Inventors: Mahantesh Narwade, Namit Gupta, Kaushik De, Rajarshi Mukherjee, Suman Nandan, Subhamoy Pal
  • Patent number: 9529948
    Abstract: A method for functional verification of a circuit description comprises generating a first set of crossover paths based on the circuit description, generating a low power information based on a power design description associated with the circuit description, the low power information determining a set of power state combinations, and generating a second set of crossover paths based on the first set of crossover paths and the low power information, the second set of crossover paths being a subset of the first set of crossover paths. Each of the second set of crossover paths is evaluated to identify circuit description errors, in particular functional circuit description errors.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: December 27, 2016
    Assignee: Synopsys, Inc.
    Inventors: Kaushik De, Mahantesh Narwade, Rajarshi Mukherjee, Namit Gupta
  • Publication number: 20150131894
    Abstract: A method for controlling the functional output of a verification tool upon receipt of a circuit description comprises searching for a predetermined base pattern in the circuit description. The method further comprises searching for predetermined sub-patterns that are assigned to the base pattern, in the circuit description. The method further comprises the validation of each found sub-pattern based on a predetermined rule to minimize the set of reported errors that based on verification of the circuit description.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 14, 2015
    Inventors: Mahantesh Narwade, Namit Gupta, Kaushik De, Rajarshi Mukherjee, Suman Nandan, Subhamoy Pal
  • Patent number: 9032339
    Abstract: Verification-result ranking techniques for root cause analysis are disclosed using violation report analysis and violation weighting. Violation reports are unwieldy and result from a variety of design and process checks. The check coverage can overlap, causing a specific violation to trigger multiple reported violations. High turn around times for violation report analysis increase the risk that selective violation analysis will inadvertently suppress real design bugs. This reduces the odds that static checker reports alone will meet design sign-off criteria. Determining relationships among a plurality of violations for a design permits clustering violations into hot spots. Identification of primary and subsequent contributors to the plurality of violations is based on the relationships among violations. The hot spot with the highest weight is identified, and then subsequent violations are identified to maximize violation coverage.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: May 12, 2015
    Assignee: Synopsys, Inc.
    Inventors: Kaushik De, Kevin M. Harer, Rajarshi Mukherjee, Mahantesh Narwade
  • Publication number: 20150121326
    Abstract: A method for functional verification of a circuit description comprises generating a first set of crossover paths based on the circuit description, generating a low power information based on a power design description associated with the circuit description, the low power information determining a set of power state combinations, and generating a second set of crossover paths based on the first set of crossover paths and the low power information, the second set of crossover paths being a subset of the first set of crossover paths. Each of the second set of crossover paths is evaluated to identify circuit description errors, in particular functional circuit description errors.
    Type: Application
    Filed: October 30, 2014
    Publication date: April 30, 2015
    Inventors: Kaushik De, Mahantesh Narwade, Rajarshi Mukherjee, Namit Gupta
  • Publication number: 20140258954
    Abstract: Verification-result ranking techniques for root cause analysis are disclosed using violation report analysis and violation weighting. Violation reports are unwieldy and result from a variety of design and process checks. The check coverage can overlap, causing a specific violation to trigger multiple reported violations. High turn around times for violation report analysis increase the risk that selective violation analysis will inadvertently suppress real design bugs. This reduces the odds that static checker reports alone will meet design sign-off criteria. Determining relationships among a plurality of violations for a design permits clustering violations into hot spots. Identification of primary and subsequent contributors to the plurality of violations is based on the relationships among violations. The hot spot with the highest weight is identified, and then subsequent violations are identified to maximize violation coverage.
    Type: Application
    Filed: March 6, 2013
    Publication date: September 11, 2014
    Applicant: SYNOPSYS, INC.
    Inventors: Kaushik De, Kevin M. Harer, Rajarshi Mukherjee, Mahantesh Narwade