Abstract: A process is disclosed for fabricating complementary n and p channel insulated gate field effect transistors. The process uses two layers of polycrystalline silicon 32 and 44 to provide electrical interconnections, and allows the formation of microcapacitors between the two layers of polycrystalline silicon. In addition silicon dioxide and silicon nitride, and two layers of photoresist, are used as masks against heavy boron implantations. The reliability of ohmic connections between aluminum 50 and contact regions in the substrate is enhanced by providing additional dopant to the contact regions. In this way, the junction depth is increased and electrical defects caused by metal spiking are minimized.

Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and self-aligned contacts for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different oxidation and etch characteristics permits selective oxidation of only desired portions of the structure without need for masking, and removal of selected material from desired locations by batch removal processes again without use of masking. The process and resulting structure affords inherently self-aligned gates and contacts for FET devices and conducting lines.