Patents by Inventor Mahdi N. Bojnordi

Mahdi N. Bojnordi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Superconducting system architecture for high-performance energy-efficient cryogenic computing
    Patent number: 10552756
    Abstract: An energy efficient rapid single flux quantum (ERSFQ) logic register wheel includes a circular shift register having a plurality of destructive read out (DRO) cells. Each entry of the circular shift register includes a data block, a tag, and a valid bit. A compare and control logic is coupled to the circular shift register to compare a source specifier or a destination register specifier against a register tag stored in the wheel following each cycle of the register wheel. At least one or more read ports and at least one or more write ports are coupled to the circular shift register to write to or to read from a different entry each in the register wheel following each cycle of the register wheel. A RSFQ clearable FIFO with flushing and a crosspoint memory topology for integrating MRAM devices with ERSFQ circuits are also described.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: February 4, 2020
    Assignee: University of Rochester
    Inventors: Engin Ipek, Ben Feinberg, Shibo Wang, Mahdi N. Bojnordi, Ravi Patel, Eby G. Friedman
  • SUPERCONDUCTING SYSTEM ARCHITECTURE FOR HIGH-PERFORMANCE ENERGY-EFFICIENT CRYOGENIC COMPUTING
    Publication number: 20190188596
    Abstract: An energy efficient rapid single flux quantum (ERSFQ) logic register wheel includes a circular shift register having a plurality of destructive read out (DRO) cells. Each entry of the circular shift register includes a data block, a tag, and a valid bit. A compare and control logic is coupled to the circular shift register to compare a source specifier or a destination register specifier against a register tag stored in the wheel following each cycle of the register wheel. At least one or more read ports and at least one or more write ports are coupled to the circular shift register to write to or to read from a different entry each in the register wheel following each cycle of the register wheel. A RSFQ clearable FIFO with flushing and a crosspoint memory topology for integrating MRAM devices with ERSFQ circuits are also described.
    Type: Application
    Filed: November 10, 2016
    Publication date: June 20, 2019
    Applicant: University of Rochester
    Inventors: Engin Ipek, Ben Feinberg, Shibo Wang, Mahdi N. Bojnordi, Ravi Patel, Eby G. Friedman