Abstract: Disclosed herein are architectures for low power, low voltage traveling wave Mach-Zehnder optical modulators. By combining single-ended series push-pull modulator configurations with differential dual-drive modulator configurations, the advantages of each type may be utilized. In particular, the halved capacitance of single-ended series push-pull modulators may reduce microwave losses, thereby improving bandwidth performance within modulator configurations. Moreover, reduced required drive voltage of dual-drive modulators coupled with increased impedance may advantageously minimize the power consumption and maximize efficiency in the differential traveling wave series push-pull Mach-Zehnder modulator configurations disclosed herein.

Abstract: Digital jitter accumulation reduction techniques and circuits are proposed to mitigate jitter accumulation in Voltage Controlled Oscillators (VCOs). In order to reduce jitter accumulation, employing a pair of identical injection locked VCOs is proposed in an interleaved fashion. Further jitter accumulation reductions can be provided by employing a plurality of identical injection locked VCOs selected in a cascading fashion. Yet further jitter accumulation reductions can be provided by resetting the deselected VCO(s).

Abstract: A circuit includes a programmable frequency divider which receives a high-speed clock, fin, as an input and which provides a modulated reference clock as an output; a Sigma-Delta modulator which receives a Frequency Control Word (FCW) and which is connected to the programmable frequency divider to receive the modulated reference clock as a sample clock and to control an average frequency of the modulated reference clock; and an integer-N Phase Lock Loop (PLL) which receives the modulated reference clock and outputs a clock output.

Abstract: Disclosed herein are architectures for low power, low voltage traveling wave Mach-Zehnder optical modulators. By combining single-ended series push-pull modulator configurations with differential dual-drive modulator configurations, the advantages of each type may be utilized. In particular, the halved capacitance of single-ended series push-pull modulators may reduce microwave losses, thereby improving bandwidth performance within modulator configurations. Moreover, reduced required drive voltage of dual-drive modulators coupled with increased impedance may advantageously minimize the power consumption and maximize efficiency in the differential traveling wave series push-pull Mach-Zehnder modulator configurations disclosed herein.

Abstract: A decision feedback equalizer (DFE) comprises four charge-steering (CS) primary latches and four primary taps. Two of the four CS primary latches are driven by complementary in-phase quarter-rate clocks and the other two of the four CS primary latches are driven by complementary quadrature quarter-rate clocks. No element of the DFE is driven by any half-rate clocks. In some implementations, each of the primary latches including a respective differential pair of n-channel output transistors and each primary tap includes a respective differential pair of p-channel input transistors connected via their gate nodes to a respective one of the four CS primary latches. In other implementations, each of the primary latches including a respective differential pair of p-channel input transistors and each primary tap includes a respective differential pair of n-channel output transistors connected via their gate nodes to a respective one of the four CS primary latches.

Abstract: A decision feedback equalizer (DFE) comprises two charge-steering (CS) input latches driven by complementary ½-rate clocks, two pairs of CS primary latches, and two pairs of taps. The primary latches are driven by ¼-rate clocks. In a first aspect, each one of the input latches and the primary latches includes a respective differential pair of n-channel output transistors, and each tap includes a respective differential pair of p-channel input transistors. In a second aspect, each one of the input latches and the primary latches includes a respective differential pair of p-channel input transistors, and each tap includes a respective differential pair of n-channel output transistors. In some implementations, no element of any one of the taps is driven by any ½-rate clock. In some implementations, every switch of at least one of the taps is driven by one of the ¼-rate clocks.

Abstract: Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.

Abstract: Digital jitter accumulation reduction techniques and circuits are proposed to mitigate jitter accumulation in Voltage Controlled Oscillators (VCOs). In order to reduce jitter accumulation, employing a pair of identical injection locked VCOs is proposed in an interleaved fashion. Further jitter accumulation reductions can be provided by employing a plurality of identical injection locked VCOs selected in a cascading fashion. Yet further jitter accumulation reductions can be provided by resetting the deselected VCO(s).

Abstract: A X-bit Digital-to-Analog Converter (DAC) circuit includes an effective X/2-bit coarse DAC configured to produce a coarse bitstream (CBS) from a digital input DC1 using an nth order Sigma-Delta (??) modulator, and to provide a coarse current source based on the CBS, wherein X is an even integer and n is an integer; an effective X/2-bit fine DAC configured to produce a fine bitstream (FBS) from a digital input DC2 using a 1st order ?? modulator, and to provide a fine current source based on the FBS; and an output configured to form a voltage from the combination of the coarse current source and the fine current source.

Abstract: A semiconductor waveguide device includes a first semiconductor layer having a first surface, wherein the first surface comprises a first protrusion and a second protrusion collectively forming a first trench in the first semiconductor layer, a second semiconductor layer having a second surface opposing the first surface of the first semiconductor layer, and an insulator layer disposed between and in contact with the first surface and the second surface, wherein the first semiconductor layer, the second semiconductor layer, and the insulator layer form a semiconductor waveguide region, and wherein the first trench is configured to confine a mode of light beam propagation in the semiconductor waveguide region.

Abstract: A controlled transconductance circuit (CTC) is disclosed. The CTC includes (i) a transistor comprising a drain terminal, a gate terminal, and a transistor source terminal, (ii) a biasing circuit element connected between the transistor source terminal and a CTC source terminal, and a variable capacitor connected between the transistor source terminal and a constant voltage terminal where the constant voltage terminal is adapted to receive a constant voltage, and (iii) a CTC control terminal adapted to control a transconductance of the CTC by controlling a capacitance of the variable capacitor.

Abstract: A controlled transconductance circuit (CTC) is disclosed. The CTC includes (i) a transistor comprising a drain terminal, a gate terminal, and a transistor source terminal, (ii) a biasing circuit element connected between the transistor source terminal and a CTC source terminal, and a variable capacitor connected between the transistor source terminal and a constant voltage terminal where the constant voltage terminal is adapted to receive a constant voltage, and (iii) a CTC control terminal adapted to control a transconductance of the CTC by controlling a capacitance of the variable capacitor.

Abstract: A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.

Abstract: A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.