Abstract: An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals.

Abstract: An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals.

Abstract: An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals.

Abstract: An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals.

Abstract: The invention offers the ability to rapidly synthesize multiple chemical compounds, particularly polymers of varying sequences, in parallel on the surfaces of carrier beads. Tinvention involves attaching up-converting phosphors (UCP's) to beads to create up-converting phosphor-loaded beads (UCP-loaded beads) with unique spectral characteristics. Using a dynamic sorting architecture each bead is cataloged based on its spectral characteristics, assigned a compound or polymer to be synthesized, and subjected to multiple rounds of sorting by a flow cytometer, wherein each round sorts the bead to an appropriate bin for a selected chemical reaction, such as the attachment of a monomeric subunit of the polymer sequence.

Abstract: A method of sampling a frequency difference in an integrated circuit is disclosed. The method comprises the steps of receiving a clock signal in a first clock domain; comparing a count of the clock signal in the first clock domain to a predetermined value N; converting the result of the comparison to a second clock domain; and generating an error signal representing the difference between the count of the first clock signal and the count of a second clock signal in the second clock domain. A circuit for sampling a frequency difference in an integrated circuit is also disclosed.

Abstract: The circuits and methods of the various embodiments of the present invention enable changing the frequency of a frequency synthesizer. According to one embodiment, a method of changing a frequency of a clock signal generated by a frequency synthesizer comprises the steps of receiving a reference clock signal; receiving a command comprising a new frequency synthesizer value; locking to a new frequency based upon the new frequency synthesizer value; and dynamically outputting a generated clock signal based upon the new frequency synthesizer value. According to another embodiment, a method of changing a frequency of a clock signal comprises adaptively adjusting the digital loop bandwidth of the frequency synthesizer. A circuit for changing a frequency of a clock signal generated in an integrated circuit is also disclosed.

Abstract: A method of generating an output of a frequency synthesizer is disclosed. The method comprises the steps of generating an output of the frequency synthesizer based upon frequency synthesizer values and a reference clock signal; receiving a command comprising a first new frequency synthesizer value; locking to a new frequency based upon the first new frequency synthesizer value; and simultaneously loading a second new frequency synthesizer value while locking to the new frequency. A circuit for generating an output of a frequency synthesizer is also disclosed.

Abstract: A circuit for frequency synthesis in an integrated circuit is described. The circuit comprises an oscillator circuit having a counter-controlled delay line. A delay register is coupled to the counter-controlled delay line. The delay register stores a delay value for the counter-controlled delay line. Finally, a phase synchronizer circuit, coupled to the oscillator circuit, controls the starting and stopping of the oscillator circuit. According to alternate embodiments, a control circuit is coupled to the oscillator circuit for changing the frequency synthesizer from a low frequency mode to a high frequency mode.

Abstract: A circuit for generating a clock signal which is frequency aligned with a reference clock signal is disclosed. The circuit comprises a phase detector coupled to receive the reference clock signal and the generated clock signal. A frequency alignment circuit generates an average frequency alignment signal based upon comparison of the phase of a generated pulse train and the phase of a reference pulse train. Finally, an oscillator control circuit is selectively coupled to receive an output of the phase detector based upon the frequency alignment signal from the frequency alignment circuit. The oscillator control circuit generating an oscillator control signal for controlling the frequency of the generated clock signal. A method of generating a clock signal which is frequency aligned with a reference clock signal is also disclosed.

Abstract: A voltage generation circuit for generating a read-back voltage in response to a supply voltage and a reference voltage. The voltage generation circuit includes a comparator configured to receive the supply voltage and the reference voltage. The voltage generation circuit activates a select signal if the supply voltage has a predetermined relationship with respect to the reference voltage, and de-activates the select signal if the supply voltage does not exhibit the predetermined relationship with respect to the reference voltage. An adjustable voltage divider circuit is coupled to receive the supply voltage and the select signal. The adjustable voltage divider circuit is configured in response to the select signal to provide an output voltage that is a first percentage of the supply voltage if the select signal is activated, and provide an output voltage that is a second percentage of the supply voltage if the select signal is de-activated.

Abstract: A method of providing a constant current drive to a driver circuit (40) in a compensating bias circuit (10) includes the steps of providing a constant current source insensitive to process, supply voltage, and temperature variations and mirroring the constant current source to the driver circuit while adding no sensitivity to process, supply voltage, and temperature variations.

Abstract: A VDD power-up detection circuit is provided having a p-channel transistor having a source coupled to a VDD voltage supply terminal and a gate coupled to a ground supply terminal. A first resistor or a diode element is coupled between the drain of the p-channel transistor and the ground supply terminal. An n-channel transistor has a source coupled to the ground supply terminal and a gate coupled to the drain of the p-channel transistor. A second resistor is coupled between a drain of the n-channel transistor and the VDD voltage supply terminal. A trigger circuit is coupled to the drain of the n-channel transistor. As the VDD supply voltage increases during power-up, the p-channel and n-channel transistors are both turned on. At this time, the trigger circuit asserts a control signal that enables an associated circuit to operate in response to the VDD supply voltage.