Abstract: In described examples, a sample and hold circuit is configured to periodically connect one input of an op-amp to a reference voltage through a switch while a second input of the op-amp is connected to an output of the op-amp. Offset cancellation is performed by storing a sampled offset on a sampling capacitor coupled to the second input of the op-amp.

Abstract: In described examples, a sample and hold circuit is configured to periodically connect one input of an op-amp to a reference voltage through a switch while a second input of the op-amp is connected to an output of the op-amp. Offset cancellation is performed by storing a sampled offset on a sampling capacitor coupled to the second input of the op-amp.

Abstract: In described examples, a sample and hold circuit is configured to periodically connect one input of an op-amp to a reference voltage through a switch while a second input of the op-amp is connected to an output of the op-amp. Offset cancellation is performed by storing a sampled offset on a sampling capacitor coupled to the second input of the op-amp.

Abstract: An analog to digital converter includes leakage current correction circuitry to cancel leakage current injected by a reset switch employing a dummy PMOS switch with a shape factor substantially similar to that of the reset switch. An operational amplifier replicates the voltage of the comparator sense input node to the drain of the dummy transistor to create the same operating point as the reset switch. The resulting leakage current is then repeated and fed back to the node to cancel the offending leakage current.

Abstract: A successive approximation register switched capacitor analog to digital converter utilizes a high frequency clock for controlling comparator reset switches and a clock distribution block to operate at lower sample rates. The successive approximation cycles are clocked with the high frequency clock so that the reset switches stay within the leakage limit irrespective of the sample rate but the end of conversion signal is delayed to mimic the slower sample rate.

Abstract: A successive approximation register switched capacitor analog to digital converter utilizes a high frequency clock for controlling comparator reset switches and a clock distribution block to operate at lower sample rates. The successive approximation cycles are clocked with the high frequency clock so that the reset switches stay within the leakage limit irrespective of the sample rate but the end of conversion signal is delayed to mimic the slower sample rate.

Abstract: An analog to digital converter includes leakage current correction circuitry to cancel leakage current injected by a reset switch employing a dummy PMOS switch with a shape factor substantially similar to that of the reset switch. An operational amplifier replicates the voltage of the comparator sense input node to the drain of the dummy transistor to create the same operating point as the reset switch. The resulting leakage current is then repeated and fed back to the node to cancel the offending leakage current.

Abstract: This invention is a clamp circuit for a video input. The clamp circuit includes: a coupling capacitor; a differential amplifier comparing a video input to predetermined reference voltage; a clamp transistor having a gate connected to the output terminal of the differential amplifier and a source-drain path connected between a power supply voltage and a second terminal; a resistive element connecting the second terminal of the clamp transistor and the coupling capacitor; a first current sink carrying a first predetermined current from the coupling capacitor to ground; and a second current sink carrying a second predetermined current from the second terminal of the said clamp transistor to ground. The resistive element can be a transistor, a resistor, a diode or a switch.

Abstract: This invention is a clamp circuit for a video input. The clamp circuit includes: a coupling capacitor; a differential amplifier comparing a video input to predetermined reference voltage; a clamp transistor having a gate connected to the output terminal of the differential amplifier and a source-drain path connected between a power supply voltage and a second terminal; a resistive element connecting the second terminal of the clamp transistor and the coupling capacitor; a first current sink carrying a first predetermined current from the coupling capacitor to ground; and a second current sink carrying a second predetermined current from the second terminal of the said clamp transistor to ground. The resistive element can be a transistor, a resistor, a diode or a switch.