Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for parallelization of GPU composition with DPU topology selection. A processor may receive an indication of a plurality of application layers for composition at a first processor (e.g., a DPU) and a second processor (e.g., a GPU). The processor may select one or more first application layers of the plurality of application layers for attempted composition at the first processor and one or more second application layers of the plurality of application layers for composition at the second processor. The processor may transmit each of the one or more first application layers to the first processor for composition and each of the one or more second application layers to the second processor for composition.

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for parallelization of GPU composition with DPU topology selection. A processor may receive an indication of a plurality of application layers for composition at a first processor (e.g., a DPU) and a second processor (e.g., a GPU). The processor may select one or more first application layers of the plurality of application layers for attempted composition at the first processor and one or more second application layers of the plurality of application layers for composition at the second processor. The processor may transmit each of the one or more first application layers to the first processor for composition and each of the one or more second application layers to the second processor for composition.

Abstract: The present disclosure relates to methods and apparatus for display processing, the apparatus configured to identify an adjustment in one or more layers of a plurality of layers in a current frame compared to layers of a plurality of layers in a previous frame; to determine, upon identifying the adjustment in the one or more layers, a first resource allocation for each of the plurality of layers; to determine, after the determination of the first resource allocation begins, a second resource allocation for each of the plurality of layers; to initiate, upon determining the first resource allocation, an execution of the composition process for each layer in the current frame based on the first resource allocation; and to initiate, upon determining the second resource allocation, an execution of the composition process for each of the layer in at least one subsequent frame based on the second resource allocation.

Abstract: The present disclosure relates to methods and devices for display processing including an apparatus, e.g., a DPU, a compositor, a compositor backend, a DPU driver, and/or DPU firmware. In some aspects, the apparatus may receive content information for each of one or more layers of a frame. The apparatus may also determine whether the content information for each of the one or more layers includes at least one priority format. Additionally, the apparatus may determine a priority order of the one or more layers when the content information for at least one of the one or more layers includes at least one priority format. The apparatus may also map each of one or more display overlay resources to each of the one or more layers based on the determined priority order of the one or more layers.

Abstract: In some aspects, the present disclosure provides a method for generating a frame. The method includes receiving a first fence indicating that a first frame stored in a display processor unit (DPU) buffer has been consumed by a hardware component. The method also includes in response to receiving the first fence, fetching a plurality of layers from an application buffer, the plurality of layers corresponding to a second frame. The method also includes determining to use both a DPU and a graphics processing unit (GPU) to process the plurality of layers for composition of the second frame. The method also includes fetching the first fence from the DPU buffer and generating a second fence.