Patents by Inventor Mahesh B. Patil

Mahesh B. Patil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8089314
    Abstract: A slew rate improved operational amplifier circuit is provided to improve the slew rates of an operational amplifier with minimal sacrifices in power dissipation and other operational amplifier parameters. To improve the slew rates of operational amplifiers, additional current sources are activated when a slewing operation is detected. The detection of slewing operations and the activation of current sources upon detection can be implemented using two comparator circuits—one for a positive slewing operation, and one for a negative slewing operation. A sub-45 nm FinFET implementation of this slew rate improvement concept was implemented and compared against slew rate optimized individual two-stage operational amplifiers. Simulations show that slew rates were significantly improved by the implementation of the comparator circuits (5590 V/?s vs. 273 V/?s), with minimal increases in power dissipation (78 ?W vs. 46 ?W).
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: January 3, 2012
    Assignee: Indian Institute of Technology-Bombay
    Inventors: Rajesh A. Thakker, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, Ramgopal V. Rao, Mahesh B. Patil
  • Publication number: 20110215868
    Abstract: A slew rate improved operational amplifier circuit is provided to improve the slew rates of an operational amplifier with minimal sacrifices in power dissipation and other operational amplifier parameters. To improve the slew rates of operational amplifiers, additional current sources are activated when a slewing operation is detected. The detection of slewing operations and the activation of current sources upon detection can be implemented using two comparator circuits—one for a positive slewing operation, and one for a negative slewing operation. A sub-45 nm FinFET implementation of this slew rate improvement concept was implemented and compared against slew rate optimized individual two-stage operational amplifiers. Simulations show that slew rates were significantly improved by the implementation of the comparator circuits (5590 V/?s vs. 273 V/?s), with minimal increases in power dissipation (78 ?W vs. 46 ?W).
    Type: Application
    Filed: April 21, 2010
    Publication date: September 8, 2011
    Applicant: Indian Institute of Technology - Bombay
    Inventors: Rajesh A. Thakker, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, Ramgopal V. Rao, Mahesh B. Patil