Patents by Inventor Mahesh Damodar BARVE

Mahesh Damodar BARVE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11736594
    Abstract: A method and system of a low-latency FPGA framework based on reliable UDP and TCP re-assembly middleware is disclosed. The need for low-latency communication in digital systems has increased drastically. The disclosed FPGA framework enables low-latency communication as a hybrid framework that supports both UDP & TCP communication. As known in art, TCP provides error checking support hence making TCP more reliable as compared to UDP, while UDP is faster but not reliable. Hence the disclosed low-latency FPGA framework latency utilizes the advantage of both UDP and TCP by utilizing UDP for its speed, while switching to TCP in case of a missing sequence in UDP. Further, the disclosed system proposes a TCP re-assembly middleware architecture for processing TCP with a lower-latency, wherein the TCP re-assembly middleware is an independent middleware that is a modular and a plug-play independent middleware.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: August 22, 2023
    Assignee: TATA CONSULTANCY SERVICES LIMITED
    Inventors: Dhaval Shah, Sunil Puranik, Manoj Nambiar, Mahesh Damodar Barve, Ishtiyaque Shaikh, Piyush Manavar, Sharyu Vijay Mukhekar
  • Patent number: 11714742
    Abstract: High level synthesis (HLS) begins with high-level specification of a problem, where behavior is generally decoupled from e.g., clock-level timing. Programming code can be run and debugged during functional simulation using debugging techniques. However, it is not possible to understand execution flow of register transfer level instructions (RTL) generated during RTL debug. Conventionally, it is challenging and not possible due to nature of debugging techniques which ignore printf statements in code for invocation. Systems and methods of present disclosure synthesize printf and/or scanf statements for generating debug messages in HLS code, wherein printf and/or scanf statements is/are included before/after function(s) in sections comprising instructions in code and synthesized as a block during run-time which communicate with host system and debug messages are generated for display on screen.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: August 1, 2023
    Assignee: TATA CONSULTANCY SERVICES LIMITED
    Inventors: Mahesh Damodar Barve, Sunil Anant Puranik, Manoj Karunakara Nambiar, Swapnil Shashikant Rodi
  • Patent number: 11611638
    Abstract: A method and system of a re-assembly middleware in FPGA for processing TCP segments into application layer messages is disclosed. In recent years, the communication speed in digital systems has increased drastically and thus has brought in a growing need to ensure a good/high performance from the FPGA services. The disclosure proposes a re-assembly middleware in the FPGA for processing TCP segments into application layer messages at a pre-defined frequency for a good/high performance. The pre-defined frequency is a high frequency performance feature of the re-assembly middleware, wherein the FPGA's implementation frequency is at atleast 300 MHz based on a memory optimization technique. The memory optimization technique includes several strategies such registering an output and slicing memories.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: March 21, 2023
    Assignee: TATA CONSULTANCY SERVICES LIMITED
    Inventors: Dhaval Shah, Sunil Puranik, Manoj Nambiar, Mahesh Damodar Barve, Ishtiyaque Shaikh
  • Publication number: 20220311839
    Abstract: A method and system of a low-latency FPGA framework based on reliable UDP and TCP re-assembly middleware is disclosed. The need for low-latency communication in digital systems has increased drastically. The disclosed FPGA framework enables low-latency communication as a hybrid framework that supports both UDP & TCP communication. As known in art, TCP provides error checking support hence making TCP more reliable as compared to UDP, while UDP is faster but not reliable. Hence the disclosed low-latency FPGA framework latency utilizes the advantage of both UDP and TCP by utilizing UDP for its speed, while switching to TCP in case of a missing sequence in UDP. Further, the disclosed system proposes a TCP re-assembly middleware architecture for processing TCP with a lower-latency, wherein the TCP re-assembly middleware is an independent middleware that is a modular and a plug-play independent middleware.
    Type: Application
    Filed: June 16, 2021
    Publication date: September 29, 2022
    Applicant: Tata Consultancy Services Limited
    Inventors: Dhaval SHAH, Sunil PURANIK, Manoj NAMBIAR, Mahesh Damodar Barve, Ishtiyaque Shaikh, Piyush Manavar, Sharyu Vijay Mukhekar
  • Publication number: 20220272178
    Abstract: A method and system of a re-assembly middleware in FPGA for processing TCP segments into application layer messages is disclosed. In recent years, the communication speed in digital systems has increased drastically and thus has brought in a growing need to ensure a good/high performance from the FPGA services. The disclosure proposes a re-assembly middleware in the FPGA for processing TCP segments into application layer messages at a pre-defined frequency for a good/high performance. The pre-defined frequency is a high frequency performance feature of the re-assembly middleware, wherein the FPGA's implementation frequency is at atleast 300 MHz based on a memory optimization technique. The memory optimization technique includes several strategies such registering an output and slicing memories.
    Type: Application
    Filed: March 22, 2021
    Publication date: August 25, 2022
    Applicant: Tata Consultancy Services Limited
    Inventors: Dhaval SHAH, Sunil PURANIK, Manoj NAMBIAR, Mahesh Damodar BARVE, Ishtiyaque SHAIKH
  • Publication number: 20220083492
    Abstract: Conventionally, for processing multi-legged orders, matching engines were implemented in software and were connected through Ethernet which is very slow in terms of throughput. Such traditional trading systems failed to process orders of tokens on different machines and these were summarily rejected. Present disclosure provides multiple FPGA system being optimized for processing/executing multi-legged orders. The system includes a plurality of FPGAs which are interconnected for communication via a PCIe port of a multi-port PCIe switch. Each FPGA comprise a net processing layer, a matcher, and a look-up table. Each FPGA is configured to process tokens (e.g., securities, etc.). If orders to be processed are for tokens on same FPGA where the order is received, then tokens are processed locally. Else net processing layer of a specific FPGA routes to specific order request to another FPGA where the tokens (securities) are located thereby reducing the latency and improving overall throughput.
    Type: Application
    Filed: December 29, 2020
    Publication date: March 17, 2022
    Applicant: Tata Consultancy Services Limited
    Inventors: Mahesh Damodar BARVE, Sunil PURANIK, Swapnil RODI, Manoj NAMBIAR, Dhaval SHAH
  • Patent number: 11263203
    Abstract: Data processing and storage is an important part of a number of applications. Conventional data processing and storage systems utilize either a full array structure or a full linked list structure for storing data wherein the array consumes large amount of memory and linked list provides slow processing. Thus, conventional systems and methods are not capable of providing simultaneous optimization of memory consumption and time efficiency. The present disclosure provides an efficient way of storing data by creating an integrated array and linked list based structure. The data is stored in the integrated array and linked list based structure by using a delta based mechanism. The delta based mechanism helps in determining the location in the integrated array and linked list based structure where the data should be stored. The present disclosure incorporates the advantages of both array and linked list structure resulting in reduced memory consumption and latency.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: March 1, 2022
    Assignee: Tata Consultancy Services Limited
    Inventors: Mahesh Damodar Barve, Sunil Anant Puranik, Manoj Nambiar, Swapnil Rodi
  • Patent number: 11263164
    Abstract: Conventionally, for processing multi-legged orders, matching engines were implemented in software and were connected through Ethernet which is very slow in terms of throughput. Such traditional trading systems failed to process orders of tokens on different machines and these were summarily rejected. Present disclosure provides multiple FPGA system being optimized for processing/executing multi-legged orders. The system includes a plurality of FPGAs which are interconnected for communication via a PCIe port of a multi-port PCIe switch. Each FPGA comprise a net processing layer, a matcher, and a look-up table. Each FPGA is configured to process tokens (e.g., securities, etc.). If orders to be processed are for tokens on same FPGA where the order is received, then tokens are processed locally. Else net processing layer of a specific FPGA routes to specific order request to another FPGA where the tokens (securities) are located thereby reducing the latency and improving overall throughput.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: March 1, 2022
    Assignee: Tata Consultancy Services Lmited
    Inventors: Mahesh Damodar Barve, Sunil Puranik, Swapnil Rodi, Manoj Nambiar, Dhaval Shah
  • Patent number: 11212218
    Abstract: The disclosure herein describes a method and a system for message based communication and failure recovery for FPGA middleware framework. A combination of FPGA and middleware framework provides a high throughput, low latency messaging and can reduce development time as most of the components can be re-used. Further the message based communication architecture built on a FPGA framework performs middleware activities that would enable reliable communication using TCP/UDP between different platforms regardless of their deployment. The proposed FPGA middleware framework provides for reliable communication of UDP based on TCP as well as failure recovery with minimum latency during a failover of an active FPGA framework during its operation, by using a passive FPGA in real-time and dynamic synchronization with the active FPGA.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: December 28, 2021
    Assignee: Tata Consultancy Services Limited
    Inventors: Manoj Karunakaran Nambiar, Swapnil Rodi, Sunil Puranik, Mahesh Damodar Barve
  • Publication number: 20210232486
    Abstract: High level synthesis (HLS) begins with high-level specification of a problem, where behavior is generally decoupled from e.g., clock-level timing. Programming code can be run and debugged during functional simulation using debugging techniques. However, it is not possible to understand execution flow of register transfer level instructions (RTL) generated during RTL debug. Conventionally, it is challenging and not possible due to nature of debugging techniques which ignore printf statements in code for invocation. Systems and methods of present disclosure synthesize printf and/or scanf statements for generating debug messages in HLS code, wherein printf and/or scanf statements is/are included before/after function(s) in sections comprising instructions in code and synthesized as a block during run-time which communicate with host system and debug messages are generated for display on screen.
    Type: Application
    Filed: December 16, 2020
    Publication date: July 29, 2021
    Applicant: Tata Consultancy Services Limited
    Inventors: Mahesh Damodar BARVE, Sunil Anant PURANIK, Manoj Karunakara NAMBIAR, Swapnil Shashikant RODI
  • Patent number: 10965519
    Abstract: This disclosure relates generally to methods and systems for providing exactly-once transaction semantics for fault tolerant FPGA based transaction systems. The systems comprise middleware components in a server as well as client end. The server comprises Hosts and FPGAs. The FPGAs control transaction execution (the application processing logic also resides in the FPGA) and provide fault tolerance with high performance by means of a modified TCP implementation. The Hosts buffer and persist transaction records for failure recovery and achieving exactly-once transaction semantics. The monitoring and fault detecting components are distributed across the FPGA's and Hosts. Exactly-once transaction semantics is implemented without sacrificing performance by switching between a high performance mode and a conservative mode depending on component failures. PCIE switches for connectivity between FPGAs and Hosts ensure FPGAs are available even if Hosts fail.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: March 30, 2021
    Assignee: TATA CONSULTANCY SERVICES LIMITED
    Inventors: Manoj Karunakaran Nambiar, Swapnil Rodi, Sunil Anant Puranik, Mahesh Damodar Barve
  • Publication number: 20200133942
    Abstract: Data processing and storage is an important part of a number of applications. Conventional data processing and storage systems utilize either a full array structure or a full linked list structure for storing data wherein the array consumes large amount of memory and linked list provides slow processing. Thus, conventional systems and methods are not capable of providing simultaneous optimization of memory consumption and time efficiency. The present disclosure provides an efficient way of storing data by creating an integrated array and linked list based structure. The data is stored in the integrated array and linked list based structure by using a delta based mechanism. The delta based mechanism helps in determining the location in the integrated array and linked list based structure where the data should be stored. The present disclosure incorporates the advantages of both array and linked list structure resulting in reduced memory consumption and latency.
    Type: Application
    Filed: October 25, 2019
    Publication date: April 30, 2020
    Applicant: Tata Consultancy Services Limited
    Inventors: Mahesh Damodar BARVE, Sunil Anant PURANIK, Manoj NAMBIAR, Swapnil RODI
  • Publication number: 20200053004
    Abstract: The disclosure herein describes a method and a system for message based communication and failure recovery for FPGA middleware framework. A combination of FPGA and middleware framework provides a high throughput, low latency messaging and can reduce development time as most of the components can be re-used. Further the message based communication architecture built on a FPGA framework performs middleware activities that would enable reliable communication using TCP/UDP between different platforms regardless of their deployment. The proposed FPGA middleware framework provides for reliable communication of UDP based on TCP as well as failure recovery with minimum latency during a failover of an active FPGA framework during its operation, by using a passive FPGA in real-time and dynamic synchronization with the active FPGA.
    Type: Application
    Filed: August 8, 2019
    Publication date: February 13, 2020
    Applicant: Tata Consultancy Services Limited
    Inventors: Manoj Karunakaran NAMBIAR, Swapnil RODI, Sunil PURANIK, Mahesh Damodar BARVE