Patents by Inventor Mahesh Jagannath Salgaonkar

Mahesh Jagannath Salgaonkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11556349
    Abstract: Methods that boot a secondary operating system (O/S) kernel with reclaimed primary kernel memory are disclosed herein. One method includes booting, via a processor performing a boot algorithm, a secondary kernel for an O/S in response to a primary kernel for the O/S going offline, in which the secondary kernel is configured to be loaded to a reserved memory area. The method further includes reclaiming memory space from the primary kernel for use in booting the secondary kernel in response to a determination that the reserved memory area includes insufficient memory space for completing the boot algorithm. Also disclosed herein are apparatus, systems, and computer program products that can include, perform, and/or implement the methods for providing a secondary kernel that includes a reserved area in memory.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: January 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Mahesh Jagannath Salgaonkar, Ananth Narayan Mavinakayanahalli, Kamalesh Babulal, Aravinda Prasad
  • Patent number: 11237891
    Abstract: Embodiments of the present disclosure facilitate handling corrected memory errors on kernel text. An example computer-implemented method includes identifying a correctable error (CE) in an error memory location of a memory and a kernel function impacted by the CE. The kernel function includes a plurality of instructions including a first instruction of the kernel function at a first physical location in a first region of the memory. The first region includes the error memory location. The plurality of instruction is loaded to a second region of the memory. The loading includes storing the first instruction of the kernel function at a second physical location in the second region of the memory. The first physical location in the first region of the memory is updated to include an instruction to branch to the second physical location in the second region of the memory.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: February 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Aravinda Prasad, Mahesh Jagannath Salgaonkar
  • Publication number: 20210279069
    Abstract: Methods that boot a secondary operating system (O/S) kernel with reclaimed primary kernel memory are disclosed herein. One method includes booting, via a processor performing a boot algorithm, a secondary kernel for an O/S in response to a primary kernel for the O/S going offline, in which the secondary kernel is configured to be loaded to a reserved memory area. The method further includes reclaiming memory space from the primary kernel for use in booting the secondary kernel in response to a determination that the reserved memory area includes insufficient memory space for completing the boot algorithm. Also disclosed herein are apparatus, systems, and computer program products that can include, perform, and/or implement the methods for providing a secondary kernel that includes a reserved area in memory.
    Type: Application
    Filed: March 4, 2020
    Publication date: September 9, 2021
    Inventors: Mahesh Jagannath Salgaonkar, Ananth Narayan Mavinakayanahalli, Kamalesh Babulal, Aravinda Prasad
  • Publication number: 20210248029
    Abstract: Embodiments of the present disclosure facilitate handling corrected memory errors on kernel text. An example computer-implemented method includes identifying a correctable error (CE) in an error memory location of a memory and a kernel function impacted by the CE. The kernel function includes a plurality of instructions including a first instruction of the kernel function at a first physical location in a first region of the memory. The first region includes the error memory location. The plurality of instruction is loaded to a second region of the memory. The loading includes storing the first instruction of the kernel function at a second physical location in the second region of the memory. The first physical location in the first region of the memory is updated to include an instruction to branch to the second physical location in the second region of the memory.
    Type: Application
    Filed: February 12, 2020
    Publication date: August 12, 2021
    Inventors: Aravinda Prasad, Mahesh Jagannath Salgaonkar