Abstract: Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is provided into a closed processing chamber, whereby a first reactant is contacted to the exposed metal surfaces to transform a top portion of the metal layer into a protective self-aligned buffer layer. Reacting molecules of the first reactant with metal atoms of this metal layer forms the protective self-aligned buffer layer entirely within such metal layer. Alternatively, adsorbing surface-active reactant molecules onto the exposed metal surface forms the protective self-aligned buffer layer. A second reactant may be contacted to the protective self-aligned buffer layer to form a self-aligned dielectric cap layer directly over the protective self-aligned buffer layer.

Abstract: Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is provided into a closed processing chamber, whereby a first reactant is contacted to the exposed metal surfaces to transform a top portion of the metal layer into a protective self-aligned buffer layer. Reacting molecules of the first reactant with metal atoms of this metal layer forms the protective self-aligned buffer layer entirely within such metal layer. Alternatively, adsorbing surface-active reactant molecules onto the exposed metal surface forms the protective self-aligned buffer layer. A second reactant may be contacted to the protective self-aligned buffer layer to form a self-aligned dielectric cap layer directly over the protective self-aligned buffer layer.

Abstract: A method is provided that conditions the chamber walls of a HDP CVD reactor by forming a layer of doped material prior to depositing dielectric layers of the doped material onto wafers. A consistent deposition rate can be maintained during subsequent deposition. When deposition is halted, the chamber is cleaned and a thin layer of the doped material is formed on the walls. Consequently, the chamber is kept at equilibrium even during periods of idle, thereby allowing the deposition rates to be consistent even after deposition resumes after the idle periods. For prolonged idle times, the chamber is re-cleaned and the doped material is re-deposited periodically, such as every 12 hours.

Abstract: A structure and method for holding a susceptor in a single-wafer RF heated CVD reactor allows the center portion of the susceptor to be heated and prevents susceptor and reactor damage due to overdriving and the susceptor from losing contact with a rotatable rod during thermal expansion. A plug, located on the bottom surface of the susceptor, heated by RF energy subsequently heats the center portion of the susceptor, thereby providing constant temperature gradients across the susceptor. The plug is connected to a rod which is contained in an upper tube and extends into a lower tube. The upper tube is connected to the susceptor via a locking mechanism. An upper spring in the upper tube applies a downward force on the upper tube such that an upward force on the bottom of the susceptor compresses the upper spring, thereby relieving stress on the susceptor and preventing damage due to overdriving.

Abstract: A CVD reactor includes separate reaction and pressure chambers, where the reaction chamber is contained within and isolates process or reactant gases from the pressure chamber. The reactor also includes a gas injection system which pre-heats and injects diffused process gas(es) into the reaction chamber in a somewhat vertical direction through a bottom surface of the reaction chamber. The gas injection system injects hydrogen or other appropriate gas in a vertical direction through the bottom surface of the reaction chamber. The flow of hydrogen or other appropriate gas is intermediate the flow of the process gas(es) and a surface of the reaction chamber, thereby re-directing the process gas flow parallel to the top surface of a wafer therein. In this manner, the reaction chamber does not require a long entry length for the process gas(es). This flow of hydrogen or other suitable gas also minimizes undesirable deposition on the surface of the reaction chamber.

Abstract: The silicon surface of a wafer is cleaned at room temperature in a separate pre-clean chamber prior to epitaxial deposition. Fluorine atoms generated, for example, from NF.sub.3 gas, enter the pre-clean chamber, contact the silicon surface, and etch away native oxide, contaminated silicon, and other damage incurred from prior wafer processes. The cleaned wafer is then transferred in an oxygen-free environment to a deposition chamber, for epitaxial deposition. By cleaning at reduced temperatures, autodoping, slip, and other stress-related problems are alleviated. By using a separate chamber for cleaning, system throughput is increased when compared to prior systems using conventional cleaning methods.

Abstract: A local area interconnect structure comprising one or more electrically conductive interconnects formed from electrically conductive metal compounds is described and a process for forming same. Electrically conductive metal compounds are selectively deposited in one or more trenches which were previously formed in an insulation layer in a configuration conforming to the desired pattern of the electrically conductive interconnects. A seed layer is first selectively formed on surfaces of the trenches and the electrically conductive metal compound is then selectively deposited over the seed layer in the trench, but not on the exposed surfaces of the insulation layer.

Abstract: A local area interconnect structure comprising one or more electrically conductive interconnects formed from electrically conductive metal compounds is described and a process for forming same. Electrically conductive metal compounds are selectively deposited in one or more trenches which were previously formed in an insulation layer in a configuration conforming to the desired pattern of the electrically conductive interconnects. A seed layer is first selectively formed on surfaces of the trenches and the electrically conductive metal compound is then selectively deposited over the seed layer in the trench, but not on the exposed surfaces of the insulation layer.

Abstract: A CVD reactor includes separate reaction and pressure chambers, where the reaction chamber is contained within and isolates reactant gases from the pressure chamber. The reactor also includes a gas injection system which injects process gas(es) into the reaction chamber in a somewhat vertical direction through a bottom surface of the reaction chamber. The gas injection system injects hydrogen or other appropriate gas in a vertical direction through the bottom surface of the reaction chamber. The flow of hydrogen or other appropriate gas is intermediate the flow of the process gas(es) and a surface of the reaction chamber, thereby re-directing the process gas flow parallel to the top surface of a wafer therein. In this manner, the reaction chamber does not require a long entry length for the process gas(es). This flow of hydrogen or other suitable gas also minimizes undesirable deposition on the surface of the reaction chamber.

Abstract: A ring is provided on a monocrystalline silicon wafer at one face thereof and adjacent the edge thereof. The ring increases the optical absorptivity of the wafer adjacent the ring compared to the optical absorptivity of the wafer distant from the ring. The ring therefore at least partially compensates for edge cooling of the wafer during rapid thermal processing thereof. Uniform thickness layers can therefore be deposited on a wafer in a rapid thermal processing system. When depositing polycrystalline silicon on an oxide covered layer, the ring may be formed as a circular trench in the oxide layer adjacent the wafer edge.

Abstract: Doped silicon-germanium alloy is selectively deposited on a semiconductor substrate, and the semiconductor substrate is then heated to diffuse at least some of the dopant from the silicon-germanium alloy into the semiconductor substrate to form a doped region at the face of the semiconductor substrate. The doped silicon-germanium alloy acts as a diffusion source for the dopant, so that shallow doped, regions may be formed at the face of the semiconductor substrate without ion implantation. A high performance contact to the doped region is also provided by forming a metal layer on the doped silicon-germanium alloy layer and heating to react at least part of the silicon-germanium alloy layer with at least part of the metal layer to form a layer of germanosilicide alloy over the doped regions. The method of the present invention is particularly suitable for forming shallow source and drain regions for a field effect transistor, and self-aligned source and drain contacts therefor.

Abstract: Doped silicon-germanium alloy is selectively deposited on a semiconductor substrate, and the semiconductor substrate is then heated to diffuse at least some of the dopant from the silicon-germanium alloy into the semiconductor substrate to form a doped region at the face of the semiconductor substrate. The doped silicon-germanium alloy acts as a diffusion source for the dopant, so that shallow doped, regions may be formed at the face of the semiconductor substrate without ion implantation. A high performance contact to the doped region is also provided by forming a metal layer on the doped silicon-germanium alloy layer and heating to react at least part of the silicon-germanium alloy layer with at least part of the metal layer to form a layer of germanosilicide alloy over the doped regions. The method of the present invention is particularly suitable for forming shallow source and drain regions for a field effect transistor, and self-aligned source and drain contacts therefor.