Patents by Inventor Mahesh M. Subedar

Mahesh M. Subedar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11936915
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: March 19, 2024
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Publication number: 20230134137
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: December 28, 2022
    Publication date: May 4, 2023
    Applicant: INTEL CORPORATION
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Patent number: 11546639
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: January 3, 2023
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Publication number: 20220021906
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: September 28, 2021
    Publication date: January 20, 2022
    Applicant: INTEL CORPORATION
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Patent number: 11172233
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: November 9, 2021
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Publication number: 20210014538
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Applicant: INTEL CORPORATION
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Patent number: 10863204
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Publication number: 20200107046
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: October 4, 2019
    Publication date: April 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Patent number: 10440395
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Patent number: 9560382
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: January 31, 2017
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Publication number: 20170013282
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: September 20, 2016
    Publication date: January 12, 2017
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Patent number: 9020046
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: April 28, 2015
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Publication number: 20140050268
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: August 6, 2013
    Publication date: February 20, 2014
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Patent number: 8482670
    Abstract: Gradient analysis may be utilized to determine frame and field repeat patterns in input video data. Those frame and field repeat patterns may then be analyzed to match them with characteristic patterns associated with telecine 3:2 and 2:2 pulldown video data, for example. In addition, a progressive detector may use combing analysis to determine whether or not a particular field is progressive or interlaced data. Then, this information, together with a field flag which indicates whether field or frame analysis is appropriate, may be utilized to distinguish telecine 2:2 or 3:2 pulldowns and interlaced and progressive data in some embodiments.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: July 9, 2013
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar
  • Publication number: 20110242424
    Abstract: Gradient analysis may be utilized to determine frame and field repeat patterns in input video data. Those frame and field repeat patterns may then be analyzed to match them with characteristic patterns associated with telecine 3:2 and 2:2 pulldown video data, for example. In addition, a progressive detector may use combing analysis to determine whether or not a particular field is progressive or interlaced data. Then, this information, together with a field flag which indicates whether field or frame analysis is appropriate, may be utilized to distinguish telecine 2:2 or 3:2 pulldowns and interlaced and progressive data in some embodiments.
    Type: Application
    Filed: June 10, 2011
    Publication date: October 6, 2011
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar
  • Patent number: 7982805
    Abstract: Gradient analysis may be utilized to determine frame and field repeat patterns in input video data. Those frame and field repeat patterns may then be analyzed to match them with characteristic patterns associated with telecine 3:2 and 2:2 pulldown video data, for example. In addition, a progressive detector may use combing analysis to determine whether or not a particular field is progressive or interlaced data. Then, this information, together with a field flag which indicates whether field or frame analysis is appropriate, may be utilized to distinguish telecine 2:2 or 3:2 pulldowns and interlaced and progressive data in some embodiments.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: July 19, 2011
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar
  • Patent number: 7983505
    Abstract: In one embodiment, the present invention includes a method for receiving pixel data for a portion of an image including a blocking artifact, calculating an artifact strength based on a difference between a two pixels on opposite sides of the blocking artifact, performing a local adaptability check using the artifact strength and values multiple pixels on the opposite sides, performing deblocking based on a result of the local adaptability check, applying a soft threshold to the artifact strength to adjust a value of the artifact strength, and re-aligning one or more pixels on the opposite sides based on the original value of the pixels and a pixel index value. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: July 19, 2011
    Assignee: Intel Corporation
    Inventors: Mahesh M. Subedar, Jorge E. Caviedes
  • Patent number: 7606423
    Abstract: A method includes detecting vertical edge pixels in an image and analyzing the detected vertical edge pixels by horizontal location in the image to detect a spatial periodicity in the detected vertical edge pixels. The method further includes detecting horizontal edge pixels in the image, and analyzing the detected horizontal edge pixels by vertical location in the image to detect a spatial periodicity in the detected horizontal edge pixels.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: October 20, 2009
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Wen-Tsung Tang, Rony Ferzli
  • Publication number: 20080240604
    Abstract: In one embodiment, the present invention includes a method for receiving pixel data for a portion of an image including a blocking artifact, calculating an artifact strength based on a difference between a two pixels on opposite sides of the blocking artifact, performing a local adaptability check using the artifact strength and values multiple pixels on the opposite sides, performing deblocking based on a result of the local adaptability check, applying a soft threshold to the artifact strength to adjust a value of the artifact strength, and re-aligning one or more pixels on the opposite sides based on the original value of the pixels and a pixel index value. Other embodiments are described and claimed.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Mahesh M. Subedar, Jorge E. Caviedes