Patents by Inventor Mahesh M. Subedar
Mahesh M. Subedar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11936915Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.Type: GrantFiled: December 28, 2022Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
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Publication number: 20230134137Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.Type: ApplicationFiled: December 28, 2022Publication date: May 4, 2023Applicant: INTEL CORPORATIONInventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
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Patent number: 11546639Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.Type: GrantFiled: September 28, 2021Date of Patent: January 3, 2023Assignee: Intel CorporationInventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
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Publication number: 20220021906Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.Type: ApplicationFiled: September 28, 2021Publication date: January 20, 2022Applicant: INTEL CORPORATIONInventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
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Patent number: 11172233Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.Type: GrantFiled: September 29, 2020Date of Patent: November 9, 2021Assignee: Intel CorporationInventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
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Publication number: 20210014538Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.Type: ApplicationFiled: September 29, 2020Publication date: January 14, 2021Applicant: INTEL CORPORATIONInventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
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Patent number: 10863204Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.Type: GrantFiled: October 4, 2019Date of Patent: December 8, 2020Assignee: Intel CorporationInventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
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Publication number: 20200107046Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.Type: ApplicationFiled: October 4, 2019Publication date: April 2, 2020Applicant: INTEL CORPORATIONInventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
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Patent number: 10440395Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.Type: GrantFiled: September 20, 2016Date of Patent: October 8, 2019Assignee: Intel CorporationInventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
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Patent number: 9560382Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.Type: GrantFiled: December 8, 2014Date of Patent: January 31, 2017Assignee: Intel CorporationInventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
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Publication number: 20170013282Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.Type: ApplicationFiled: September 20, 2016Publication date: January 12, 2017Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
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Patent number: 9020046Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.Type: GrantFiled: August 6, 2013Date of Patent: April 28, 2015Assignee: Intel CorporationInventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
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Publication number: 20140050268Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.Type: ApplicationFiled: August 6, 2013Publication date: February 20, 2014Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
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Patent number: 8482670Abstract: Gradient analysis may be utilized to determine frame and field repeat patterns in input video data. Those frame and field repeat patterns may then be analyzed to match them with characteristic patterns associated with telecine 3:2 and 2:2 pulldown video data, for example. In addition, a progressive detector may use combing analysis to determine whether or not a particular field is progressive or interlaced data. Then, this information, together with a field flag which indicates whether field or frame analysis is appropriate, may be utilized to distinguish telecine 2:2 or 3:2 pulldowns and interlaced and progressive data in some embodiments.Type: GrantFiled: June 10, 2011Date of Patent: July 9, 2013Assignee: Intel CorporationInventors: Jorge E. Caviedes, Mahesh M. Subedar
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Publication number: 20110242424Abstract: Gradient analysis may be utilized to determine frame and field repeat patterns in input video data. Those frame and field repeat patterns may then be analyzed to match them with characteristic patterns associated with telecine 3:2 and 2:2 pulldown video data, for example. In addition, a progressive detector may use combing analysis to determine whether or not a particular field is progressive or interlaced data. Then, this information, together with a field flag which indicates whether field or frame analysis is appropriate, may be utilized to distinguish telecine 2:2 or 3:2 pulldowns and interlaced and progressive data in some embodiments.Type: ApplicationFiled: June 10, 2011Publication date: October 6, 2011Inventors: Jorge E. Caviedes, Mahesh M. Subedar
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Patent number: 7982805Abstract: Gradient analysis may be utilized to determine frame and field repeat patterns in input video data. Those frame and field repeat patterns may then be analyzed to match them with characteristic patterns associated with telecine 3:2 and 2:2 pulldown video data, for example. In addition, a progressive detector may use combing analysis to determine whether or not a particular field is progressive or interlaced data. Then, this information, together with a field flag which indicates whether field or frame analysis is appropriate, may be utilized to distinguish telecine 2:2 or 3:2 pulldowns and interlaced and progressive data in some embodiments.Type: GrantFiled: September 26, 2005Date of Patent: July 19, 2011Assignee: Intel CorporationInventors: Jorge E. Caviedes, Mahesh M. Subedar
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Patent number: 7983505Abstract: In one embodiment, the present invention includes a method for receiving pixel data for a portion of an image including a blocking artifact, calculating an artifact strength based on a difference between a two pixels on opposite sides of the blocking artifact, performing a local adaptability check using the artifact strength and values multiple pixels on the opposite sides, performing deblocking based on a result of the local adaptability check, applying a soft threshold to the artifact strength to adjust a value of the artifact strength, and re-aligning one or more pixels on the opposite sides based on the original value of the pixels and a pixel index value. Other embodiments are described and claimed.Type: GrantFiled: March 30, 2007Date of Patent: July 19, 2011Assignee: Intel CorporationInventors: Mahesh M. Subedar, Jorge E. Caviedes
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Patent number: 7606423Abstract: A method includes detecting vertical edge pixels in an image and analyzing the detected vertical edge pixels by horizontal location in the image to detect a spatial periodicity in the detected vertical edge pixels. The method further includes detecting horizontal edge pixels in the image, and analyzing the detected horizontal edge pixels by vertical location in the image to detect a spatial periodicity in the detected horizontal edge pixels.Type: GrantFiled: September 29, 2005Date of Patent: October 20, 2009Assignee: Intel CorporationInventors: Jorge E. Caviedes, Mahesh M. Subedar, Wen-Tsung Tang, Rony Ferzli
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Publication number: 20080240604Abstract: In one embodiment, the present invention includes a method for receiving pixel data for a portion of an image including a blocking artifact, calculating an artifact strength based on a difference between a two pixels on opposite sides of the blocking artifact, performing a local adaptability check using the artifact strength and values multiple pixels on the opposite sides, performing deblocking based on a result of the local adaptability check, applying a soft threshold to the artifact strength to adjust a value of the artifact strength, and re-aligning one or more pixels on the opposite sides based on the original value of the pixels and a pixel index value. Other embodiments are described and claimed.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Inventors: Mahesh M. Subedar, Jorge E. Caviedes