Patents by Inventor Mahesh Maddury
Mahesh Maddury has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11681611Abstract: Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.Type: GrantFiled: December 11, 2020Date of Patent: June 20, 2023Assignee: Intel CorporationInventors: Omid Azizi, Amin Firoozshahian, Andreas Kleen, Mahesh Madhav, Mahesh Maddury, Chandan Egbert, Eric Gouldey
-
Patent number: 11392491Abstract: Processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms.Type: GrantFiled: June 27, 2018Date of Patent: July 19, 2022Assignee: Intel CorporationInventors: Amin Firoozshahian, Omid Azizi, Chandan Egbert, David Hansen, Andreas Kleen, Mahesh Maddury, Mahesh Madhav, Alexandre Solomatnikov, John Peter Stevenson
-
Patent number: 11169929Abstract: A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page faults. The memory management circuitry includes an express invalidations circuitry, and a page translation permission circuitry. The memory management circuitry is to, while the core is executing the instructions, receive a command to pause communication between the I/O device and the memory. In response to receiving the command to pause the communication, modify permissions of page translations by the page translation permission circuitry and transmit an invalidation request, by the express invalidations circuitry to the I/O device, to cause cached page translations in the I/O device to be invalidated.Type: GrantFiled: April 20, 2018Date of Patent: November 9, 2021Assignee: INTEL CORPORATIONInventors: Rupin Vakharwala, Amin Firoozshahian, Stephen Van Doren, Rajesh Sankaran, Mahesh Madhav, Omid Azizi, Andreas Kleen, Mahesh Maddury, Ashok Raj
-
Publication number: 20210240609Abstract: Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.Type: ApplicationFiled: December 11, 2020Publication date: August 5, 2021Inventors: Omid Azizi, Amin Firoozshahian, Andreas Kleen, Mahesh Madhav, Mahesh Maddury, Chandan Egbert, Eric Gouldey
-
Patent number: 10866888Abstract: Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.Type: GrantFiled: January 11, 2018Date of Patent: December 15, 2020Assignee: Intel CorporationInventors: Omid Azizi, Amin Firoozshahian, Andreas Kleen, Mahesh Madhav, Mahesh Maddury, Chandan Egbert, Eric Gouldey
-
Patent number: 10732880Abstract: Various systems and methods for computer memory management are described herein. A system for computer memory management includes a first memory device including a mapping table; a second memory device including a staging area; a third memory device including a dedup data region; and a controller operable to: receive a memory access request, the memory access request including an address and data; write the data to the staging area; and update the mapping table with the address.Type: GrantFiled: January 11, 2018Date of Patent: August 4, 2020Assignee: Intel CorporationInventors: Omid Azizi, Amin Firoozshahian, John Stevenson, Mahesh Maddury, Chandan Egbert, Henk Neefs
-
Patent number: 10579551Abstract: Various systems and methods for computer memory management are described herein. A system includes a memory controller to: monitor utilization of a memory device, the memory device used with a memory compression technique; determine that the utilization of the memory device violates a threshold; and initiate a system interrupt to provoke a response, responsive to the utilization of the memory device violating the threshold.Type: GrantFiled: December 27, 2017Date of Patent: March 3, 2020Assignee: Intel CorporationInventors: Ishwar Agarwal, Omid Azizi, Chandan Egbert, Amin Firoozshahian, David Christopher Hansen, Andreas Kleen, Mahesh Maddury, Mahesh Madhav, Ashok Raj, Alexandre Solomatnikov, Stephen Van Doren
-
Publication number: 20200004677Abstract: Processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms.Type: ApplicationFiled: June 27, 2018Publication date: January 2, 2020Inventors: Amin Firoozshahian, Omid Azizi, Chandan Egbert, David Hansen, Andreas Kleen, Mahesh Maddury, Mahesh Madhav, Alexandre Solomatnikov, John Peter Stevenson
-
Publication number: 20190303281Abstract: Various systems and methods for controlling memory traffic flow rate are described herein. A system for computer memory management, the system comprising: rate control circuitry to: receive a rate exceeded signal from monitoring circuitry, the rate exceeded signal indicating that memory traffic flow from a traffic source exceeds a threshold; receive a distress signal from a memory controller that interfaces with a memory device, the distress signal indicating that the memory device is oversubscribed; and implement throttle circuitry to throttle the memory traffic flow from the traffic source when the rate exceeded signal and the distress signal are both asserted.Type: ApplicationFiled: March 30, 2018Publication date: October 3, 2019Inventors: Amin Firoozshahian, Vedaraman Greetha, Andreas Kleen, Stephen Van Doren, Omid Azizi, Mahesh Madhav, Mahesh Maddury, Chandan Egbert
-
Publication number: 20190213120Abstract: Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.Type: ApplicationFiled: January 11, 2018Publication date: July 11, 2019Inventors: Omid Azizi, Amin Firoozshahian, Andreas Kleen, Mahesh Madhav, Mahesh Maddury, Chandan Egbert, Eric Gouldey
-
Publication number: 20190212935Abstract: Various systems and methods for computer memory management are described herein. A system for computer memory management includes a first memory device including a mapping table; a second memory device including a staging area; a third memory device including a dedup data region; and a controller operable to: receive a memory access request, the memory access request including an address and data; write the data to the staging area; and update the mapping table with the address.Type: ApplicationFiled: January 11, 2018Publication date: July 11, 2019Inventors: Chandan Egbert, Amin Firoozshahian, Mahesh Maddury, John Stevenson, Henk Neefs, Omid Azizi
-
Publication number: 20190196988Abstract: Various systems and methods for computer memory management are described herein. A system includes a memory controller to: monitor utilization of a memory device, the memory device used with a memory compression technique; determine that the utilization of the memory device violates a threshold; and initiate a system interrupt to provoke a response, responsive to the utilization of the memory device violating the threshold.Type: ApplicationFiled: December 27, 2017Publication date: June 27, 2019Inventors: Ishwar Agarwal, Omid Azizi, Chandan Egbert, Amin Firoozshahian, David Christopher Hansen, Andreas Kleen, Mahesh Maddury, Mahesh Madhav, Ashok Raj, Alexandre Solomatnikov, Stephen Van Doren
-
Publication number: 20190042461Abstract: A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page faults. The memory management circuitry includes an express invalidations circuitry, and a page translation permission circuitry. The memory management circuitry is to, while the core is executing the instructions, receive a command to pause communication between the I/O device and the memory. In response to receiving the command to pause the communication, modify permissions of page translations by the page translation permission circuitry and transmit an invalidation request, by the express invalidations circuitry to the I/O device, to cause cached page translations in the I/O device to be invalidated.Type: ApplicationFiled: April 20, 2018Publication date: February 7, 2019Inventors: Rupin Vakharwala, Amin Firoozshahian, Stephen Van Doren, Rajesh Sankaran, Mahesh Madhav, Omid Azizi, Andreas Kleen, Mahesh Maddury, Ashok Raj
-
Publication number: 20180004668Abstract: A searchable hot content cache stores frequently accessed data values in accordance with embodiments. In one embodiment, a circuit includes interface circuitry to receive memory requests from a processor. The circuit includes hardware logic to determine that a number of the memory requests that is to access a value meets or exceeds a threshold. The circuit includes a storage array to store the value in an entry based on a determination that the number meets or exceeds the threshold. In response to receipt of a memory request from the processor to access the same value at a memory address, the hardware logic is to map the memory address to the entry of the storage array.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: Omid J. AZIZI, Alexandre Y. SOLOMATNIKOV, Amin FIROOZSHAHIAN, John P. STEVENSON, Mahesh MADDURY
-
Patent number: 8873558Abstract: In one embodiment, a method includes receiving a packet at an interface at a network device having a plurality of interfaces connected to a plurality of links forming a bundle, performing a Reverse Path Forwarding (RPF) check on the received packet, and forwarding the packet if it passes the RPF check. The RPF check includes a lookup in an RPF table having a plurality of entries for the bundle, each of the entries including the bundle and one of the links in the bundle, and verification that the interface receiving the packet is connected to one of the links in the bundle identified in the lookup. An apparatus is also disclosed.Type: GrantFiled: August 3, 2011Date of Patent: October 28, 2014Assignee: Cisco Technology, Inc.Inventors: Sarang Dharmapurikar, Mahesh Maddury, Francisco Matus
-
Publication number: 20130064246Abstract: Techniques are provided for forwarding packets via an intermediate network device. A packet comprising a destination MAC address is received at a first port of a network device having a plurality of bi-directional ports. A second port of the network device to which the packet should be forwarded is identified through the use of at least an approximate ingress table at the first port comprising a plurality of compressed destination MAC addresses each having an associated egress port, and the packet is forwarded to the second port. At the second port, a subsequent network device to which the packet should be forwarded is identified through the use of an exact egress table at the second port including exact destination MAC addresses each associated with a network device connected to the second port, and the packet is forwarded to the subsequent network device.Type: ApplicationFiled: September 12, 2011Publication date: March 14, 2013Applicant: CISCO TECHNOLOGY, INC.Inventors: Sarang Dharmapurikar, Kit Chiu Chu, Mahesh Maddury, Dinesh G. Dutt, Francisco Matus
-
Publication number: 20130034097Abstract: In one embodiment, a method includes receiving a packet at an interface at a network device having a plurality of interfaces connected to a plurality of links forming a bundle, performing a Reverse Path Forwarding (RPF) check on the received packet, and forwarding the packet if it passes the RPF check. The RPF check includes a lookup in an RPF table having a plurality of entries for the bundle, each of the entries including the bundle and one of the links in the bundle, and verification that the interface receiving the packet is connected to one of the links in the bundle identified in the lookup. An apparatus is also disclosed.Type: ApplicationFiled: August 3, 2011Publication date: February 7, 2013Applicant: CISCO TECHNOLOGY, INC.Inventors: Sarang Dharmapurikar, Mahesh Maddury, Francisco Matus
-
Patent number: 8249069Abstract: In one embodiment, a method includes receiving a multi-destination packet at a switch in communication with a plurality of servers through a network device, identifying a port receiving the multi-destination packet at the switch or a forwarding topology for the multi-destination packet, selecting a bit value based on the identified port or forwarding topology, inserting the bit value into a field in a virtual network tag in the multi-destination packet, and forwarding the multi-destination packet with the virtual network tag to the network device. The network device is configured to forward the multi-destination packet to one or more of the servers based on the bit value in the multi-destination packet. An apparatus for forwarding multi-destination packets is also disclosed.Type: GrantFiled: March 30, 2010Date of Patent: August 21, 2012Assignee: Cisco Technology, Inc.Inventors: Pirabhu Raman, Dinesh Dutt, Mahesh Maddury, Subbarao Arumilli, Vijay Rangarajan, Ray Kloth, Sanjay Sane
-
Publication number: 20110243136Abstract: In one embodiment, a method includes receiving a multi-destination packet at a switch in communication with a plurality of servers through a network device, identifying a port receiving the multi-destination packet at the switch or a forwarding topology for the multi-destination packet, selecting a bit value based on the identified port or forwarding topology, inserting the bit value into a field in a virtual network tag in the multi-destination packet, and forwarding the multi-destination packet with the virtual network tag to the network device. The network device is configured to forward the multi-destination packet to one or more of the servers based on the bit value in the multi-destination packet. An apparatus for forwarding multi-destination packets is also disclosed.Type: ApplicationFiled: March 30, 2010Publication date: October 6, 2011Applicant: CISCO TECHNOLOGY, INC.Inventors: Pirabhu Raman, Dinesh Dutt, Mahesh Maddury, Subbarao Arumilli, Vijay Rangarajan, Ray Kloth, Sanjay Sane