Patents by Inventor Mahesh Madhavan
Mahesh Madhavan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230396264Abstract: High speed, high dynamic range SAR ADC method and architecture. The SAR DAC comparison method can make fewer comparisons with less charge/fewer capacitors. The architecture makes use of a modified top plate switching (TPS) DAC technique and therefore achieves very high-speed operation. The present disclosure proffers a unique SAR ADC method of input and reference capacitor DAC switching. This benefits in higher dynamic range, no external decoupling capacitory requirement, wide common mode range and overall faster operation due to the absence of mini-ADC.Type: ApplicationFiled: June 1, 2022Publication date: December 7, 2023Applicant: Analog Devices International Unlimited CompanyInventor: Mahesh Madhavan Kumbaranthodiyil
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Patent number: 11711094Abstract: High speed, high dynamic range SAR ADC method and architecture. The SAR DAC comparison method can make fewer comparisons with less charge/fewer capacitors. The architecture makes use of a modified top plate switching (TPS) DAC technique and therefore achieves very high-speed operation. The present disclosure proffers a unique SAR ADC method of input and reference capacitor DAC switching. This benefits in higher dynamic range, no external decoupling capacitory requirement, wide common mode range and overall faster operation due to the absence of mini-ADC.Type: GrantFiled: December 22, 2021Date of Patent: July 25, 2023Assignee: Analog Devices International Unlimited CompanyInventor: Mahesh Madhavan Kumbaranthodiyil
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Publication number: 20230198541Abstract: High speed, high dynamic range SAR ADC method and architecture. The SAR DAC comparison method can make fewer comparisons with less charge/fewer capacitors. The architecture makes use of a modified top plate switching (TPS) DAC technique and therefore achieves very high-speed operation. The present disclosure proffers a unique SAR ADC method of input and reference capacitor DAC switching. This benefits in higher dynamic range, no external decoupling capacitory requirement, wide common mode range and overall faster operation due to the absence of mini-ADC.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Applicant: Analog Devices International Unlimited CompanyInventor: Mahesh Madhavan KUMBARANTHODIYIL
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Patent number: 10862502Abstract: Techniques are described that can be used to extract an offset and a gain of a signal chain, which can be used for digital correction of an analog-to-digital converter (ADC) output to help achieve a life time and temperature stable ADC output. For example, using various techniques, a value for a voltage reference VREF and a value for ground (GND) (or other reference voltage) can be converted, which can then be used to determine gain and offset, respectively, of the signal chain.Type: GrantFiled: November 21, 2019Date of Patent: December 8, 2020Assignee: Analog Devices International Unlimited CompanyInventors: Mahesh Madhavan Kumbaranthodiyil, Kirubakaran Ramalingam
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Patent number: 10848172Abstract: An IC can include shared reference voltage buffer circuitry having an amplifier circuit. A commonly-routed amplifier shared output voltage node can be shared between at least two digital-to-analog converters (DACs) respectively via at least first and second individually routed traces from the shared output voltage node to respective first and second local reference voltage nodes at the DACs. Respective first and second routing trace resistances can be based on current draw of the corresponding DAC, such as to provide an equal voltage drop across the first and second routing resistances. This can help avoid voltage contention or conflict at the shared output voltage node from forcing/sensing the voltages at the first and second local reference voltage nodes. In a further example, at least one of the first and second individually routed traces can include a binary tree hierarchical routing arrangement of at least some of the DACs.Type: GrantFiled: December 5, 2019Date of Patent: November 24, 2020Assignee: Analog Devices International Unlimited CompanyInventors: Kirubakaran Ramalingam, Ayan Das, Hrishikesh Ravi Mathukkarumukku, Mahesh Madhavan Kumbaranthodiyil
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Publication number: 20200287558Abstract: Techniques are described that can be used to extract an offset and a gain of a signal chain, which can be used for digital correction of an analog-to-digital converter (ADC) output to help achieve a life time and temperature stable ADC output. For example, using various techniques, a value for a voltage reference VREF and a value for ground (GND) (or other reference voltage) can be converted, which can then be used to determine gain and offset, respectively, of the signal chain.Type: ApplicationFiled: November 21, 2019Publication date: September 10, 2020Inventors: Mahesh Madhavan Kumbaranthodiyil, Kirubakaran Ramalingam
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Publication number: 20200287561Abstract: An IC can include shared reference voltage buffer circuitry having an amplifier circuit. A commonly-routed amplifier shared output voltage node can be shared between at least two digital-to-analog converters (DACs) respectively via at least first and second individually routed traces from the shared output voltage node to respective first and second local reference voltage nodes at the DACs. Respective first and second routing trace resistances can be based on current draw of the corresponding DAC, such as to provide an equal voltage drop across the first and second routing resistances. This can help avoid voltage contention or conflict at the shared output voltage node from forcing/sensing the voltages at the first and second local reference voltage nodes. In a further example, at least one of the first and second individually routed traces can include a binary tree hierarchical routing arrangement of at least some of the DACs.Type: ApplicationFiled: December 5, 2019Publication date: September 10, 2020Inventors: Kirubakaran Ramalingam, Ayan Das, Hrishikesh Ravi Mathukkarumukku, Mahesh Madhavan Kumbaranthodiyil
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Patent number: 10615812Abstract: A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.Type: GrantFiled: January 31, 2019Date of Patent: April 7, 2020Assignee: Analog Devices Global Unlimited CompanyInventors: Sandeep Monangi, Mahesh Madhavan
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Publication number: 20190173478Abstract: A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.Type: ApplicationFiled: January 31, 2019Publication date: June 6, 2019Inventors: Sandeep Monangi, Mahesh Madhavan
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Patent number: 10256831Abstract: A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.Type: GrantFiled: September 21, 2016Date of Patent: April 9, 2019Assignee: Analog Devices GlobalInventors: Sandeep Monangi, Mahesh Madhavan
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Patent number: 10200041Abstract: An analog multiplexer may be used for sampling an input voltage that is capable of having a higher voltage level than an upper supply voltage. The analog multiplexer includes a plurality of input switch circuits and a shorting switch circuit. The plurality of input switch circuits include n-type or p-type laterally diffused field effect transistors (NLDFETs or PLDFETs). At least one of the input switch circuits includes a level shifting switch circuit that is able to sample an input voltage that is greater than the upper supply voltage for the multiplexer. A shorting switch circuit, at an output of the multiplexer, includes a capacitively coupled gate drive circuit and is configured to short a first differential output to a second differential output after the input voltage is sampled.Type: GrantFiled: November 1, 2016Date of Patent: February 5, 2019Assignee: Analog Devices GlobalInventors: Jeremy R. Gorbold, Christian Steffen Birk, Gerard Mora Puchalt, Colin Charles Price, Michael C. W. Coln, Mahesh Madhavan Kumbaranthodiyil
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Publication number: 20180123591Abstract: An analog multiplexer may be used for sampling an input voltage that is capable of having a higher voltage level than an upper supply voltage. The analog multiplexer includes a plurality of input switch circuits and a shorting switch circuit. The plurality of input switch circuits include n-type or p-type laterally diffused field effect transistors (NLDFETs or PLDFETs). At least one of the input switch circuits includes a level shifting switch circuit that is able to sample an input voltage that is greater than the upper supply voltage for the multiplexer. A shorting switch circuit, at an output of the multiplexer, includes a capacitively coupled gate drive circuit and is configured to short a first differential output to a second differential output after the input voltage is sampled.Type: ApplicationFiled: November 1, 2016Publication date: May 3, 2018Inventors: Jeremy R. Gorbold, Christian Steffen Birk, Gerard Mora Puchalt, Colin Charles Price, Michael C.W. Coln, Mahesh Madhavan Kumbaranthodiyil
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Publication number: 20180083645Abstract: A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.Type: ApplicationFiled: September 21, 2016Publication date: March 22, 2018Inventors: Sandeep Monangi, Mahesh Madhavan
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Patent number: 9791880Abstract: Methods and apparatus to reduce localized transistor operating temperature increases in fully integrated voltage regulator circuits are provided. Transistor self-heating effects are reduced by dispersing heat more evenly over the integrated circuit die, via use of nested voltage regulator circuits and/or use of more than one transistor in a voltage regulator circuit pass device. An electrically parallel-connected group of multiple individual integrated transistors may be laid out across cooler areas of the integrated circuit die, such as in substantially linear sets or rings of devices near the outer die perimeter. Each transistor in the group may better disperse its own heat if it is thermally segregated from other self-heating devices, as through a minimum physical layout spacing. Transistor bias voltage mismatch tolerances, load currents, and routing resistances may interrelatedly determine the number of individual transistors needed in a group.Type: GrantFiled: March 16, 2016Date of Patent: October 17, 2017Assignee: Analog Devices GlobalInventors: Mahesh Madhavan Kumbaranthodiyil, Jeremy R. Gorbold
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Publication number: 20170269623Abstract: Methods and apparatus to reduce localized transistor operating temperature increases in fully integrated voltage regulator circuits are provided. Transistor self-heating effects are reduced by dispersing heat more evenly over the integrated circuit die, via use of nested voltage regulator circuits and/or use of more than one transistor in a voltage regulator circuit pass device. An electrically parallel-connected group of multiple individual integrated transistors may be laid out across cooler areas of the integrated circuit die, such as in substantially linear sets or rings of devices near the outer die perimeter. Each transistor in the group may better disperse its own heat if it is thermally segregated from other self-heating devices, as through a minimum physical layout spacing. Transistor bias voltage mismatch tolerances, load currents, and routing resistances may interrelatedly determine the number of individual transistors needed in a group.Type: ApplicationFiled: March 16, 2016Publication date: September 21, 2017Inventors: Mahesh Madhavan Kumbaranthodiyil, Jeremy R. Gorbold
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Publication number: 20160105194Abstract: In an example embodiment, an analog to digital converter (ADC) facilitating passive analog sample and hold is provided and includes a pair of binary weighted conversion capacitor arrays, a pair of sampling capacitors, and a plurality of switches that configure each conversion capacitor array and the sampling capacitors for a sampling phase, a charge transfer phase, and a bit trial phase. During the sampling phase, the sampling capacitors are decoupled from the conversion capacitors and coupled to an analog input voltage. During the charge transfer phase, the sampling capacitors are coupled to the conversion capacitors and decoupled from the analog input voltage. During the bit trial phase, the sampling capacitors are decoupled from the conversion capacitors.Type: ApplicationFiled: October 10, 2014Publication date: April 14, 2016Applicant: ANALOG DEVICES TECHNOLOGYInventors: MAHESH MADHAVAN KUMBARANTHODIYIL, Sandeep Monangi
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Patent number: 7839319Abstract: The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.Type: GrantFiled: October 20, 2008Date of Patent: November 23, 2010Assignee: Analog Devices, Inc.Inventors: Srikanth Nittala, Jeremy Gorbold, Mahesh Madhavan
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Publication number: 20090102694Abstract: The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.Type: ApplicationFiled: October 20, 2008Publication date: April 23, 2009Inventors: Srikanth Nittala, Jeremy Gorbold, Mahesh Madhavan
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Patent number: 7439898Abstract: The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.Type: GrantFiled: May 31, 2007Date of Patent: October 21, 2008Assignee: Analog Devices, Inc.Inventors: Srikanth Nittala, Jeremy Gorbold, Mahesh Madhavan