Patents by Inventor Mahesh Madhukar Mehendale
Mahesh Madhukar Mehendale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230273972Abstract: A technique for controlling a processing device. The technique includes receiving, from a first register, input feature values. The technique also includes receiving, from a second register, weight values. The technique further includes receiving first addresses of output registers. The technique also includes performing a matrix multiplication of the input feature values and weight values in parallel to obtain matrix multiplication results. The technique further includes providing the matrix multiplication results to the output registers.Type: ApplicationFiled: February 28, 2022Publication date: August 31, 2023Inventors: Mahesh Madhukar MEHENDALE, Uri WEINRIB, Avi Sammy BERKOVICH
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Patent number: 11551745Abstract: A device includes a comparator to provide an indication of a difference between Vp on a first terminal coupled to a top plate of each of a first group of differential capacitors, and Vn on a second terminal coupled to a top plate of each of a second group of differential capacitors. The device includes a control circuit coupled to the comparator. The control circuit is to receive a first indication of a difference between Vp and Vn; responsive to the first indication, cause a first driver to provide a reference voltage to bottom plates of one of the first and second groups, and cause a second driver to provide a ground voltage to bottom plates of the other of the first and second groups; receive a second indication of a difference between Vp and Vn; and provide a digital value responsive to the first indication and the second indication.Type: GrantFiled: January 29, 2021Date of Patent: January 10, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Avishek Biswas, Mahesh Madhukar Mehendale
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Publication number: 20220408106Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.Type: ApplicationFiled: August 23, 2022Publication date: December 22, 2022Inventors: Hetul Sanghvi, Mihir Narendra Mody, Niraj Nandan, Mahesh Madhukar Mehendale, Subrangshu Das, Dipan Kumar Mandal, Nainala Vyagrheswarudu, Vijayavardhan Baireddy, Pavan Venkata Shastry
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Patent number: 11445207Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.Type: GrantFiled: December 16, 2019Date of Patent: September 13, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Hetul Sanghvi, Mihir Narendra Mody, Niraj Nandan, Mahesh Madhukar Mehendale, Subrangshu Das, Dipan Kumar Mandal, Nainala Vyagrheswarudu, Vijayavardhan Baireddy, Pavan Venkata Shastry
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Publication number: 20220108203Abstract: In a memory device, a static random access memory (SRAM) circuit includes an array of SRAM cells arranged in rows and columns and configured to store data. The SRAM array is configured to: store a first set of information for a machine learning (ML) process in a lookup table in the SRAM array; and consecutively access, from the lookup table, information from a selected set of the SRAM cells along a row of the SRAM cells. A memory controller circuit is configured to select the set of the SRAM cells based on a second set of information for the ML process.Type: ApplicationFiled: October 1, 2020Publication date: April 7, 2022Inventors: Mahesh Madhukar MEHENDALE, Vinod Joseph MENEZES
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Publication number: 20210240441Abstract: A device includes a bit cell having first and second terminals, a first bit line coupled to the first terminal, a second bit line coupled to the second terminal, a first capacitor, a second capacitor, and a multiply and average (MAV) circuit coupled to the first capacitor, to the second capacitor, to the first bit line, and to the second bit line. The MAV circuit includes a first transistor coupled to the first capacitor and to a ground terminal and a second transistor coupled to the second capacitor and to the ground terminal. The first transistor has a first transistor control terminal selectively coupled to the first bit line and the second transistor has a second transistor control terminal selectively coupled to the second bit line.Type: ApplicationFiled: January 29, 2021Publication date: August 5, 2021Inventors: Avishek BISWAS, Mahesh Madhukar MEHENDALE, Hetul SANGHVI
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Publication number: 20210241820Abstract: A device includes a comparator to provide an indication of a difference between Vp on a first terminal coupled to a top plate of each of a first group of differential capacitors, and Vn on a second terminal coupled to a top plate of each of a second group of differential capacitors. The device includes a control circuit coupled to the comparator. The control circuit is to receive a first indication of a difference between Vp and Vn; responsive to the first indication, cause a first driver to provide a reference voltage to bottom plates of one of the first and second groups, and cause a second driver to provide a ground voltage to bottom plates of the other of the first and second groups; receive a second indication of a difference between Vp and Vn; and provide a digital value responsive to the first indication and the second indication.Type: ApplicationFiled: January 29, 2021Publication date: August 5, 2021Inventors: Avishek BISWAS, Mahesh Madhukar MEHENDALE
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Patent number: 10855184Abstract: A switch-mode power supply includes a DC-DC converter and metering circuitry that is coupled to the DC-DC converter. The metering circuitry includes scaling circuitry, a current source, a capacitor, switching circuitry, and a comparator. The scaling circuitry is configured to generate a reference current scaled to be a predetermined fraction of a peak current flowing in an inductor of the DC-DC converter. The current source is configured to output a first current that is one-half of the reference current. The capacitor is coupled to the current source. The switching circuitry is configured to switchably connect the current source to the capacitor. The comparator is coupled to the capacitor. The comparator is configured to generate a signal indicating that a voltage across the capacitor exceeds a threshold voltage.Type: GrantFiled: October 14, 2019Date of Patent: December 1, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vinod Joseph Menezes, Manikandan Rr, Rajat Chauhan, Vipul Kumar Singhal, Mahesh Madhukar Mehendale, Kaichien Tsai
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Publication number: 20200204075Abstract: A switch-mode power supply includes a DC-DC converter and metering circuitry that is coupled to the DC-DC converter. The metering circuitry includes scaling circuitry, a current source, a capacitor, switching circuitry, and a comparator. The scaling circuitry is configured to generate a reference current scaled to be a predetermined fraction of a peak current flowing in an inductor of the DC-DC converter. The current source is configured to output a first current that is one-half of the reference current. The capacitor is coupled to the current source. The switching circuitry is configured to switchably connect the current source to the capacitor. The comparator is coupled to the capacitor. The comparator is configured to generate a signal indicating that a voltage across the capacitor exceeds a threshold voltage.Type: ApplicationFiled: October 14, 2019Publication date: June 25, 2020Inventors: Vinod Joseph MENEZES, Manikandan RR, Rajat CHAUHAN, Vipul Kumar SINGHAL, Mahesh Madhukar MEHENDALE, Kaichien TSAI
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Publication number: 20200120351Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Hetul Sanghvi, Mihir Narendra Mody, Niraj Nandan, Mahesh Madhukar Mehendale, Subrangshu Das, Dipan Kumar Mandal, Nainala Vyagrheswarudu, Vijayavardhan Baireddy, Pavan Venkata Shastry
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Patent number: 10601408Abstract: In described examples, a sawtooth waveform generator generates a sawtooth waveform having a first rise time. A comb waveform circuit has a power terminal coupled to receive the sawtooth waveform from an output of the sawtooth waveform generator. The comb waveform circuit generates a comb waveform in response to the sawtooth waveform. The comb waveform has a second rise time that is faster than the first rise time.Type: GrantFiled: April 13, 2018Date of Patent: March 24, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajat Chauhan, Vipul Kumar Singhal, Vinod Joseph Menezes, Mahesh Madhukar Mehendale
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Patent number: 10547859Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.Type: GrantFiled: July 19, 2017Date of Patent: January 28, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Hetul Sanghvi, Mihir Narendra Mody, Niraj Nandan, Mahesh Madhukar Mehendale, Subrangshu Das, Dipan Kumar Mandal, Nainala Vyagrheswarudu, Vijayavardhan Baireddy, Pavan Venkata Shastry
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Publication number: 20190319614Abstract: In described examples, a sawtooth waveform generator generates a sawtooth waveform having a first rise time. A comb waveform circuit has a power terminal coupled to receive the sawtooth waveform from an output of the sawtooth waveform generator. The comb waveform circuit generates a comb waveform in response to the sawtooth waveform. The comb waveform has a second rise time that is faster than the first rise time.Type: ApplicationFiled: April 13, 2018Publication date: October 17, 2019Inventors: Rajat Chauhan, Vipul Kumar Singhal, Vinod Joseph Menezes, Mahesh Madhukar Mehendale
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Patent number: 10447142Abstract: A switch-mode power supply includes a DC-DC converter and metering circuitry that is coupled to the DC-DC converter. The metering circuitry includes scaling circuitry, a current source, a capacitor, switching circuitry, and a comparator. The scaling circuitry is configured to generate a reference current scaled to be a predetermined fraction of a peak current flowing in an inductor of the DC-DC converter. The current source is configured to output a first current that is one-half of the reference current. The capacitor is coupled to the current source. The switching circuitry is configured to switchably connect the current source to the capacitor. The comparator is coupled to the capacitor. The comparator is configured to generate a signal indicating that a voltage across the capacitor exceeds a threshold voltage.Type: GrantFiled: December 20, 2018Date of Patent: October 15, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vinod Joseph Menezes, Manikandan RR, Rajat Chauhan, Vipul Kumar Singhal, Mahesh Madhukar Mehendale, Kaichien Tsai
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Patent number: 10397591Abstract: A control processor for a video encode-decode engine is provided that includes an instruction pipeline. The instruction pipeline includes an instruction fetch stage coupled to an instruction memory to fetch instructions, an instruction decoding stage coupled to the instruction fetch stage to receive the fetched instructions, and an execution stage coupled to the instruction decoding stage to receive and execute decoded instructions. The instruction decoding stage and the instruction execution stage are configured to decode and execute a set of instructions in an instruction set of the control processor that are designed specifically for accelerating video sequence encoding and encoded video bit stream decoding.Type: GrantFiled: April 11, 2015Date of Patent: August 27, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dipan Kumar Mandal, Mihir Narendra Mody, Mahesh Madhukar Mehendale, Chaitanya Satish Ghone, Piyali Goswami, Naresh Kumar Yadav, Hetul Sanghvi, Niraj Nandan
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Patent number: 9973754Abstract: A low power video hardware engine is disclosed. The video hardware engine includes a video hardware accelerator unit. A shared memory is coupled to the video hardware accelerator unit, and a scrambler is coupled to the shared memory. A vDMA (video direct memory access) engine is coupled to the scrambler, and an external memory is coupled to the vDMA engine. The scrambler receives an LCU (largest coding unit) from the vDMA engine. The LCU comprises N×N pixels, and the scrambler scrambles N×N pixels in the LCU to generate a plurality of blocks with M×M pixels. N and M are integers and M is less than N.Type: GrantFiled: March 18, 2015Date of Patent: May 15, 2018Assignee: Texas Instruments IncorporatedInventors: Hetul Sanghvi, Mihir Narendra Mody, Niraj Nandan, Mahesh Madhukar Mehendale, Subrangshu Das, Dipan Kumar Mandal, Pavan Venkata Shastry
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Publication number: 20170318304Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.Type: ApplicationFiled: July 19, 2017Publication date: November 2, 2017Inventors: Hetul Sanghvi, Mihir Narendra Mody, Niraj Nandan, Mahesh Madhukar Mehendale, Subrangshu Das, Dipan Kumar Mandal, Nainala Vyagrheswarudu, Vijayavardhan Baireddy, Pavan Venkata Shastry
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Publication number: 20150296212Abstract: A control processor for a video encode-decode engine is provided that includes an instruction pipeline. The instruction pipeline includes an instruction fetch stage coupled to an instruction memory to fetch instructions, an instruction decoding stage coupled to the instruction fetch stage to receive the fetched instructions, and an execution stage coupled to the instruction decoding stage to receive and execute decoded instructions. The instruction decoding stage and the instruction execution stage are configured to decode and execute a set of instructions in an instruction set of the control processor that are designed specifically for accelerating video sequence encoding and encoded video bit stream decoding.Type: ApplicationFiled: April 11, 2015Publication date: October 15, 2015Inventors: Dipan Kumar Mandal, Mihir Narendra Mody, Mahesh Madhukar Mehendale, Chaitanya Satish Ghone, Piyali Goswami, Naresh Kumar Yadav, Hetul Sanghvi, Niraj Nandan
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Publication number: 20150271494Abstract: A low power video hardware engine is disclosed. The video hardware engine includes a video hardware accelerator unit. A shared memory is coupled to the video hardware accelerator unit, and a scrambler is coupled to the shared memory. A vDMA (video direct memory access) engine is coupled to the scrambler, and an external memory is coupled to the vDMA engine. The scrambler receives an LCU (largest coding unit) from the vDMA engine. The LCU comprises N×N pixels, and the scrambler scrambles N×N pixels in the LCU to generate a plurality of blocks with M×M pixels. N and M are integers and M is less than N.Type: ApplicationFiled: March 18, 2015Publication date: September 24, 2015Inventors: Hetul Sanghvi, Mihir Narendra Mody, Niraj Nandan, Mahesh Madhukar Mehendale, Subrangshu Das, Dipan Kumar Mandal, Pavan Venkata Shastry
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Publication number: 20150271512Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.Type: ApplicationFiled: March 18, 2015Publication date: September 24, 2015Inventors: Hetul Sanghvi, Mihir Narendra Mody, Niraj Nandan, Mahesh Madhukar Mehendale, Subrangshu Das, Dipan Kumar Mandal, Nainala Vyagrheswarudu, Vijayavardhan Baireddy, Pavan Venkata Shastry