Abstract: Aspects for high speed USB data routing are presented. The aspects include routing a data stream to and from USB I/O ports serially, and maintaining a frequency of the data stream during the routing. Additionally, a root port router is provided for the root port and a data port router is provided for each I/O port, wherein each data port router delays the data stream by one bit during the routing.

Abstract: Aspects of efficient modeling of a differential bus device in an ASIC library include utilizing a hardware description language (HDL) to model a differential bus device. A mapping scheme based on signal strengths of the HDL is utilized to represent a set of differential bus signals as single bits during simulation of the differential bus device. Further, the differential bus device comprises a USB device, and the HDL comprises Verilog.

Abstract: Aspects for high speed USB data routing are presented. The aspects include routing a data stream to and from USB I/O ports serially, and maintaining a frequency of the data stream during the routing. Additionally, a root port router is provided for the root port and a data port router is provided for each I/O port, wherein each data port router delays the data stream by one bit during the routing.

Abstract: A versatile USB controller comprises a serial interface engine (SIE) for connection with a host. The SIE is capable of simulating a disconnect/connect sequence in situations where a reboot of the device is appropriate. The controller further includes a control store for keeping track of multiple endpoints of a device. A FIFO provides data transfer between each of the endpoints and the host. A state machine provides transaction sequencing with the host for each endpoint. In a variation of the preferred embodiment, a second FIFO is included to provide additional buffering capability.

Abstract: A method and apparatus for improving bandwidth of sequential access to a display data memory. Display data and tag information related to consecutive data repetitions are stored. No display memory access is needed to output data to the CRT during the time periods when data is being repeated, thus increasing display memory bandwidth. Display data from a location in display memory is stored in a latch, and is output from the latch until the tag information indicates no more data repetitions occur.