Patents by Inventor Mahesh TANNIRU

Mahesh TANNIRU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11973657
    Abstract: A system may receive enterprise information associated with a client enterprise. The system may select, using an industry analysis model, a set of queries associated with obtaining status information that is associated with a technology profile of the client enterprise. The system may generate client data that is associated with the enterprise information and the status information. The system may convert, using a matrix factorization technique, the client data associated with the client enterprise to a client matrix. The system may convert, using the matrix factorization technique, reference data associated with reference enterprises to a reference matrix. The system may determine, based on a comparison of the client matrix and the reference matrix, a set of scores associated with technology metrics of the technology profile. The system may perform an action associated with the client enterprise based on the set of scores.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: April 30, 2024
    Assignee: Accenture Global Solutions Limited
    Inventors: Rajendra Tanniru Prasad, Bhaskar Ghosh, Aditi Kulkarni, Koushik M. Vijayaraghavan, Purnima Jagannathan, Parul Jagtap, Sangeetha Jayaram, Badrinath Parameswar, Manas Mishra, Jeffson Felix Dsouza, Gaurav Goenka, Gaurav Sood, Pradeep Senapati, Vaijayanthi Ramaswamy, Ranjith Tharayil, Mahesh Zurale, Ramanathan Venkataraman
  • Publication number: 20230369207
    Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a first conductive line and a second conductive line in a first dielectric layer, the second conductive line laterally spaced apart from the first conductive line. The integrated circuit structure also includes a first conductive via and a second conductive via in a second dielectric layer, the second dielectric layer over the first dielectric layer, the second conductive via laterally spaced apart from the first conductive via, the first conductive via vertically over and connected to the first conductive line, and the second conductive via vertically over but separated from the second conductive line.
    Type: Application
    Filed: May 13, 2022
    Publication date: November 16, 2023
    Inventors: Clifford J. ENGEL, Robert L. BRISTOL, Richard H. LIVENGOOD, Mahesh TANNIRU, Akshit PEER, Mauro J. KOBRINSKY, Kevin Lai LIN