Patents by Inventor Mahesh U. Wagh

Mahesh U. Wagh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method to maximize buffer utilization in an I/O controller
    Patent number: 9378173
    Abstract: An apparatus and method for maximizing buffer utilization in an I/O controller using credit management logic contained within the I/O controller. The credit management logic keeps track of the number of memory credits available in the I/O controller and communicates to a chipset connected to the I/O controller the amount of available memory credits. The chipset may then send an amount of data to the I/O controller equivalent to or less than the communicated available amount of memory credits to reduce the occurrence of a “retry” event. The amount of available memory credits is determined by comparing the available memory in each buffer within the I/O controller and designating that the “available” amount of memory for the I/O controller is an amount equivalent to the amount of memory contained in the buffer with the least amount of available memory. This “available” amount of I/O controller memory may then be converted into memory credits and communicated to the chipset.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: June 28, 2016
    Assignee: Intel Corporation
    Inventors: Mahesh U. Wagh, Wilfred W. Kwok, Sridhar Muthrasanallur
  • Apparatus and Method to Maximize Buffer Utilization in an I/O Controller
    Publication number: 20100146162
    Abstract: An apparatus and method for maximizing buffer utilization in an I/O controller using credit management logic contained within the I/O controller. The credit management logic keeps track of the number of memory credits available in the I/O controller and communicates to a chipset connected to the I/O controller the amount of available memory credits. The chipset may then send an amount of data to the I/O controller equivalent to or less than the communicated available amount of memory credits to reduce the occurrence of a “retry” event. The amount of available memory credits is determined by comparing the available memory in each buffer within the I/O controller and designating that the “available” amount of memory for the I/O controller is an amount equivalent to the amount of memory contained in the buffer with the least amount of available memory. This “available” amount of I/O controller memory may then be converted into memory credits and communicated to the chipset.
    Type: Application
    Filed: February 11, 2010
    Publication date: June 10, 2010
    Inventors: Mahesh U. Wagh, Wilfred W. Kwok, Sridhar Muthrasanallur
  • Apparatus to maximize buffer utilization in an I/O controller
    Patent number: 7734847
    Abstract: An apparatus and method for maximizing buffer utilization in an I/O controller using credit management logic contained within the I/O controller. The credit management logic keeps track of the number of memory credits available in the I/O controller and communicates to a chipset connected to the I/O controller the amount of available memory credits. The chipset may then send an amount of data to the I/O controller equivalent to or less than the communicated available amount of memory credits to reduce the occurrence of a “retry” event. The amount of available memory credits is determined by comparing the available memory in each buffer within the I/O controller and designating that the “available” amount of memory for the I/O controller is an amount equivalent to the amount of memory contained in the buffer with the least amount of available memory. This “available” amount of I/O controller memory may then be converted into memory credits and communicated to the chipset.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: June 8, 2010
    Assignee: Intel Corporation
    Inventors: Mahesh U. Wagh, Wilfred W. Kwok, Sridhar Muthrasanallur
  • Apparatus and method to maximize buffer utilization in an I/O controller
    Patent number: 7441055
    Abstract: An apparatus and method for maximizing buffer utilization in an I/O controller using credit management logic contained within the I/O controller. The credit management logic keeps track of the number of memory credits available in the I/O controller and communicates to a chipset connected to the I/O controller the amount of available memory credits. The chipset may then send an amount of data to the I/O controller equivalent to or less than the communicated available amount of memory credits to reduce the occurrence of a “retry” event. The amount of available memory credits is determined by comparing the available memory in each buffer within the I/O controller and designating that the “available” amount of memory for the I/O controller is an amount equivalent to the amount of memory contained in the buffer with the least amount of available memory. This “available” amount of I/O controller memory may then be converted into memory credits and communicated to the chipset.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: October 21, 2008
    Assignee: Intel Corporation
    Inventors: Mahesh U. Wagh, Wilfred W. Kwok, Sridhar Muthrasanallur
  • Apparatus and Method to Maximize Buffer Utilization in an I/O Controller
    Publication number: 20080235413
    Abstract: An apparatus and method for maximizing buffer utilization in an I/O controller using credit management logic contained within the I/O controller. The credit management logic keeps track of the number of memory credits available in the I/O controller and communicates to a chipset connected to the I/O controller the amount of available memory credits. The chipset may then send an amount of data to the I/O controller equivalent to or less than the communicated available amount of memory credits to reduce the occurrence of a “retry” event. The amount of available memory credits is determined by comparing the available memory in each buffer within the I/O controller and designating that the “available” amount of memory for the I/O controller is an amount equivalent to the amount of memory contained in the buffer with the least amount of available memory. This “available” amount of I/O controller memory may then be converted into memory credits and communicated to the chipset.
    Type: Application
    Filed: April 30, 2008
    Publication date: September 25, 2008
    Inventors: Mahesh U. Wagh, Wilfred W. Kwok, Sridhar Muthrasanallur