Patents by Inventor Mahesh Veerina

Mahesh Veerina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6424659
    Abstract: Multilayer switching device and associated technique enables simultaneous wire-speed routing at OSI layer 3, wire-speed switching at layer 2, and support multiple interfaces at layer 1. Implementation may be embodied using one or more integrated circuits (ASIC), RISC processor, and software, thereby providing wire-speed performance on interfaces, in various operational modes.
    Type: Grant
    Filed: July 17, 1998
    Date of Patent: July 23, 2002
    Assignee: Network Equipment Technologies, Inc.
    Inventors: Krishna Viswanadham, Mahesh Veerina
  • Publication number: 20010043614
    Abstract: Multilayer switching device and associated technique enables simultaneous wire-speed routing at OSI layer 3, wire-speed switching at layer 2, and support multiple interfaces at layer 1. Implementation may be embodied using one or more integrated circuits (ASIC), RISC processor, and software, thereby providing wire-speed performance on interfaces, in various operational modes.
    Type: Application
    Filed: July 17, 1998
    Publication date: November 22, 2001
    Inventors: KRISHNA VISWANADHAM, MAHESH VEERINA
  • Patent number: 6243379
    Abstract: Router circuit, provides Internet protocol (IP) address translation to enable connection or packet-level multiplexing over multiple single-user IP address account links. Connection-level multiplexing (CLM) provide between LAN and WAN addresses outbound packet transfer by replacing private packet source IP address and port number with said external IP address port number, and inbound packet transfer by replacing external packet destination IP address and port number with private IP address and port number. Look-up table provides bi-directional translation or effective multiplexing of IP addresses and port assignments for incoming or outgoing packets. Packet-level multiplexing (PLM) provides between LAN1 and LAN2 addresses outbound packet processing, wherein destination IP address and port number are replaced with external IP address and port number, and inbound packet processing, wherein source IP address and port number are replaced with internal IP address and port number.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: June 5, 2001
    Assignee: Ramp Networks, Inc.
    Inventors: Mahesh Veerina, Suresh Gurajapu, Raghu Bathina