Patents by Inventor Mahesh Wagh
Mahesh Wagh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12001353Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.Type: GrantFiled: August 12, 2022Date of Patent: June 4, 2024Assignee: Intel CorporationInventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
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Patent number: 11971841Abstract: An adapter is provided that includes a first interface to couple to a particular device, where link layer data is to be communicated over the first interface, and a second interface to couple to a physical layer (PHY) device. The PHY device includes wires to implement a physical layer of a link, and the link couples the adapter to another adapter via the PHY device. The second interface includes a data channel to communicate the link layer data over the physical layer, and a sideband channel to communicate sideband messages between the adapter and the other adapter over the physical layer. The adapter is to implement a logical PHY for the link.Type: GrantFiled: August 31, 2020Date of Patent: April 30, 2024Assignee: Intel CorporationInventors: Narasimha Lanka, Swadesh Choudhary, Mahesh Wagh, Lakshmipriya Seshan
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Publication number: 20240020259Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.Type: ApplicationFiled: July 14, 2023Publication date: January 18, 2024Applicant: Intel CorporationInventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
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Patent number: 11797378Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.Type: GrantFiled: April 14, 2022Date of Patent: October 24, 2023Assignee: Intel CorporationInventors: Venkatraman Iyer, Robert G. Blankenship, Mahesh Wagh, Zuoguo Wu
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Patent number: 11726939Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.Type: GrantFiled: September 25, 2021Date of Patent: August 15, 2023Assignee: Intel CorporationInventors: Debendra Das Sharma, Michelle C. Jen, Prahladachar Jayaprakash Bharadwaj, Bruce Tennant, Mahesh Wagh
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Patent number: 11729096Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.Type: GrantFiled: August 2, 2021Date of Patent: August 15, 2023Assignee: Intel CorporationInventors: Debendra Das Sharma, Michelle C. Jen, Mark S. Myers, Don Soltis, Ramacharan Sundararaman, Stephen R. Van Doren, Mahesh Wagh
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Patent number: 11663154Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.Type: GrantFiled: April 15, 2022Date of Patent: May 30, 2023Assignee: Intel CorporationInventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
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Publication number: 20230073807Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.Type: ApplicationFiled: July 8, 2022Publication date: March 9, 2023Applicant: Intel CorporationInventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
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Publication number: 20230026906Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.Type: ApplicationFiled: August 12, 2022Publication date: January 26, 2023Inventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
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Publication number: 20220350769Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.Type: ApplicationFiled: April 15, 2022Publication date: November 3, 2022Applicant: Intel CorporationInventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
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Publication number: 20220350698Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.Type: ApplicationFiled: April 14, 2022Publication date: November 3, 2022Applicant: Intel CorporationInventors: Venkatraman Iyer, Robert G. Blankenship, Mahesh Wagh, Zuoguo Wu
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Patent number: 11442876Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.Type: GrantFiled: May 30, 2019Date of Patent: September 13, 2022Assignee: Intel CorporationInventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
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Patent number: 11386033Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.Type: GrantFiled: December 14, 2020Date of Patent: July 12, 2022Assignee: Intel CorporationInventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
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Patent number: 11307928Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.Type: GrantFiled: July 24, 2020Date of Patent: April 19, 2022Assignee: Intel CorporationInventors: Venkatraman Iyer, Robert G. Blankenship, Mahesh Wagh, Zuoguo Wu
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Patent number: 11308018Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.Type: GrantFiled: September 9, 2020Date of Patent: April 19, 2022Assignee: Intel CorporationInventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
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Patent number: 11245604Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols and each comprising one of a serial link protocol, a coherent link protocol, and an accelerator link protocol, cause processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol, and cause processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol.Type: GrantFiled: November 18, 2020Date of Patent: February 8, 2022Assignee: INTEL CORPORATIONInventors: Mahesh Wagh, Mark S. Myers, Stephen R. Van Doren, Dimitrios Ziakas, Bassam N. Coury
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Publication number: 20220012203Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.Type: ApplicationFiled: September 25, 2021Publication date: January 13, 2022Applicant: Intel CorporationInventors: Debendra Das Sharma, Michelle C. Jen, Prahladachar Jayaprakash Bharadwaj, Bruce A. Tennant, Mahesh Wagh
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Publication number: 20210399982Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.Type: ApplicationFiled: August 2, 2021Publication date: December 23, 2021Inventors: Debendra Das Sharma, Michelle C. Jen, Mark S. Myers, Don Soltis, Ramacharan Sundararaman, Stephen R. Van Doren, Mahesh Wagh
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Patent number: 11144492Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.Type: GrantFiled: March 6, 2020Date of Patent: October 12, 2021Assignee: Intel CorporationInventors: Debendra Das Sharma, Michelle C. Jen, Prahladachar Jayaprakash Bharadwaj, Bruce A. Tennant, Mahesh Wagh
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Patent number: 11113225Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.Type: GrantFiled: June 5, 2020Date of Patent: September 7, 2021Assignee: Intel CorporationInventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss