Abstract: A power intent may be loaded on an integrated circuit (IC) design, where the power intent may be represented by a set of constraints. A logic network may be constructed based on the set of constraints and a rule check which is desired to be performed on the power intent. In response to a failure of the rule check, one or more refutation proofs may be created based on the logic network. A subset of the set of constraints may be identified based on the one or more refutation proofs, where the subset of the set of constraints may include an inconsistency which caused the rule check to fail.

Abstract: A netlist is updated based on an engineering change order (ECO) circuit network by determining primary cuts of a first network of a netlist and secondary cuts of the ECO circuit network. The primary cuts are at least a portion of the first network, and include one or more logic elements and an output node. The secondary cuts are a least a portion of the ECO circuit network, and include one or more logic elements and an output node. Further, matching cuts are determined from the primary cuts and the secondary cuts. The matching cuts include a first cut of the primary cuts and a second cut of the secondary cuts. A downward frontier of the ECO circuit network is determined from the matching cuts, and the netlist is updated based on the downward frontier.

Abstract: Disclosed approaches for processing a circuit design include identifying a driver and a load having a hold violation in the circuit design. The circuit design is targeted to an integrated circuit (IC) die. The method determines a first offset from a location on a perimeter of a rectangular region of the IC die having corners at locations of the driver and the load such that a length of a signal path from the driver through a first candidate location having placement coordinates that are outside the rectangular region and at the first offset from the location on the perimeter resolves the hold violation. The method determines availability of the first candidate location. In response to determining that the first candidate location is available, the method includes instantiating a delay circuit at the first candidate location and specifying connections that connect the delay circuit between the driver and the load.