Patents by Inventor Maheswaren Surendra

Maheswaren Surendra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CMOS silicide metal gate integration
    Patent number: 7655557
    Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: February 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaren Surendra
  • CMOS SILICIDE METAL GATE INTEGRATION
    Publication number: 20080254622
    Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
    Type: Application
    Filed: June 24, 2008
    Publication date: October 16, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaren Surendra
  • CMOS silicide metal gate integration
    Patent number: 7411227
    Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: August 12, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaren Surendra
  • Method, apparatus and program product for software provisioning
    Publication number: 20070294376
    Abstract: A software provisioning model which effectively combines characteristics of both push and pull models. In response to a request, a server sends a workflow or recipe of actions along with code server parameters and a requesting client computer system executes the,workflow and pulls necessary software updates and services to the client.
    Type: Application
    Filed: June 20, 2006
    Publication date: December 20, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Naga A. Ayachitula, Larisa Shwartz, Maheswaren Surendra
  • CMOS silicide metal gate integration
    Publication number: 20060189061
    Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
    Type: Application
    Filed: April 19, 2006
    Publication date: August 24, 2006
    Inventors: Ricky Amos, Diane Boyd, Cyril Cabral, Richard Kaplan, Jakub Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda Mocuta, Vijay Narayanan, An Steegen, Maheswaren Surendra